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riscv: Fix rounding mode setting.
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parent
9157d992ac
commit
df313bd296
4 changed files with 39 additions and 5 deletions
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@ -115,9 +115,6 @@ static const IRMeta irMeta[] = {
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{ IROp::FpCtrlFromReg, "FpCtrlFromReg", "_G" },
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{ IROp::FpCtrlToReg, "FpCtrlToReg", "G" },
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{ IROp::VfpuCtrlToReg, "VfpuCtrlToReg", "GI" },
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{ IROp::RestoreRoundingMode, "RestoreRoundingMode", "" },
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{ IROp::ApplyRoundingMode, "ApplyRoundingMode", "" },
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{ IROp::UpdateRoundingMode, "UpdateRoundingMode", "" },
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{ IROp::SetCtrlVFPU, "SetCtrlVFPU", "TC" },
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{ IROp::SetCtrlVFPUReg, "SetCtrlVFPUReg", "TG" },
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{ IROp::SetCtrlVFPUFReg, "SetCtrlVFPUFReg", "TF" },
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@ -695,10 +695,11 @@ bool PropagateConstants(const IRWriter &in, IRWriter &out, const IROptions &opts
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}
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break;
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case IROp::FpCtrlFromReg:
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gpr.MapIn(inst.src1);
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gpr.MapDirtyIn(IRREG_FCR31, inst.src1);
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gpr.MapDirty(IRREG_FPCOND);
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goto doDefault;
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case IROp::FpCtrlToReg:
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gpr.MapDirty(inst.dest);
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gpr.MapDirtyInIn(inst.dest, IRREG_FPCOND, IRREG_FCR31);
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goto doDefault;
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case IROp::Vec4Init:
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@ -115,6 +115,40 @@ void RiscVJit::CompIR_Transfer(IRInst inst) {
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gpr.SetImm(IRREG_FPCOND, 0);
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break;
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case IROp::FpCtrlFromReg:
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gpr.MapDirtyIn(IRREG_FPCOND, inst.src1, MapType::AVOID_LOAD_MARK_NORM32);
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LI(SCRATCH1, 0x0181FFFF);
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AND(SCRATCH1, gpr.R(inst.src1), SCRATCH1);
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// Extract the new fpcond value.
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if (cpu_info.RiscV_Zbs) {
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BEXTI(gpr.R(IRREG_FPCOND), SCRATCH1, 23);
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} else {
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SRLI(gpr.R(IRREG_FPCOND), SCRATCH1, 23);
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ANDI(gpr.R(IRREG_FPCOND), gpr.R(IRREG_FPCOND), 1);
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}
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SW(SCRATCH1, CTXREG, IRREG_FCR31 * 4);
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break;
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case IROp::FpCtrlToReg:
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gpr.MapDirtyIn(inst.dest, IRREG_FPCOND, MapType::AVOID_LOAD_MARK_NORM32);
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// Load fcr31 and clear the fpcond bit.
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LW(SCRATCH1, CTXREG, IRREG_FCR31 * 4);
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if (cpu_info.RiscV_Zbs) {
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BCLRI(SCRATCH1, SCRATCH1, 23);
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} else {
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LI(SCRATCH2, ~(1 << 23));
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AND(SCRATCH1, SCRATCH1, SCRATCH2);
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}
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// Now get the correct fpcond bit.
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ANDI(SCRATCH2, gpr.R(IRREG_FPCOND), 1);
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SLLI(SCRATCH2, SCRATCH2, 23);
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OR(gpr.R(inst.dest), SCRATCH1, SCRATCH2);
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// Also update mips->fcr31 while we're here.
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SW(gpr.R(inst.dest), CTXREG, IRREG_FCR31 * 4);
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break;
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case IROp::VfpuCtrlToReg:
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gpr.MapDirtyIn(inst.dest, IRREG_VFPU_CTRL_BASE + inst.src1);
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MV(gpr.R(inst.dest), gpr.R(IRREG_VFPU_CTRL_BASE + inst.src1));
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@ -291,6 +291,8 @@ void RiscVJit::CompileIRInst(IRInst inst) {
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case IROp::SetCtrlVFPUFReg:
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case IROp::FpCondToReg:
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case IROp::ZeroFpCond:
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case IROp::FpCtrlFromReg:
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case IROp::FpCtrlToReg:
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case IROp::VfpuCtrlToReg:
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case IROp::FMovFromGPR:
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case IROp::FMovToGPR:
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