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4766 commits

Author SHA1 Message Date
Unknown W. Brackets
7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00
Unknown W. Brackets
d092f7dd2d armjit: Remember reg imm values even after flush. 
This way, we can base other imm values off them, or even do imm math using
them.  We can also avoid re-flushing an imm.
 2013-11-10 15:50:14 -08:00
Unknown W. Brackets
7f9cbc0f10 armjit: Minor cleanup and logging tweaks. 2013-11-10 15:12:40 -08:00
Unknown W. Brackets
455a7e090d Compile the cache instruction to nothing. 
Was showing up in a few profiles, does nothing currently.
 2013-11-10 14:38:10 -08:00
Unknown W. Brackets
1cc68f50ca armjit: Small optimization to syscall instr. 2013-11-10 14:38:10 -08:00
Unknown W. Brackets
b30928036e armjit: Avoid flushing an imm in beq/bne/etc. 
We might be able to STMIA it instead.
 2013-11-10 14:38:10 -08:00
Unknown W. Brackets
285ec1fad5 armjit: Implement mult/multu for immediates. 
Uncommon, but may reduce instructions a bit.
 2013-11-10 14:38:09 -08:00
Unknown W. Brackets
3a8f0598c4 x86jit: Implement wsbh/wsbw. 2013-11-10 14:38:09 -08:00
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9bec82873c armjit: inline byteswaps of imm values. 2013-11-10 14:38:08 -08:00
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06c8cb9174 armjit: Do shifts with imms as much as possible. 
This may even make an imm operand2 safe that wasn't before.
 2013-11-10 14:38:08 -08:00
Sacha
f29d9c0bf9 Blackberry: fix freezing due to overflow of nanoseconds in timer. 2013-11-11 04:53:08 +10:00
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b2c2a87511 Fix omitted CC_AL reset, fixes #4498. 
Was breaking non-fastmem lwl/lwr/etc.
 2013-11-10 09:24:40 -08:00
Henrik Rydgård
cc23635843 Merge pull request #4495 from unknownbrackets/multithread 
Fix some issues in multithreading on Android
 2013-11-10 01:56:50 -08:00
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d6048dc646 Don't burn the cpu while idle in multithread. 2013-11-09 23:08:45 -08:00
Unknown W. Brackets
113146302b Don't schedule a finish event when not running. 
Otherwise it'll get it when it does run, and stop early.
 2013-11-09 23:08:44 -08:00
Unknown W. Brackets
afafa5fcd6 Make sure the gpu thread has a chance to run. 
If the scheduler puts it on the same core, it may not even do anything
before we check if the framebuffer is dirty, so SyncThread will quit since
it's not even running.

Instead, let's wait until it's at least done something.
 2013-11-09 23:08:28 -08:00
Unknown W. Brackets
879060f008 Use a CORE_POWERUP state when starting. 
Otherwise, we could startup in CORE_POWERDOWN in a second game, which is
confusing.
 2013-11-09 23:07:52 -08:00
shenweip
0a9cf9b1bc Turn up logging. 2013-11-10 10:40:56 +08:00
Unknown W. Brackets
b310edc5f8 Fix typo in ARM debug build. 2013-11-09 15:58:27 -08:00
Henrik Rydgard
d1c012d75e ARM: Open up all 32 accessible VFP registers if NEON is available. 2013-11-09 20:18:20 +01:00
Henrik Rydgård
70a239ba47 Merge pull request #4486 from unknownbrackets/debugger 
Use a shortcut for copying instructions, enable G3D log always
 2013-11-09 11:08:12 -08:00
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712b582d26 Remove coreParam.disableG3Dlog and enableDebugging. 
One was uninitialized, the other one unused.
 2013-11-09 11:02:12 -08:00
Henrik Rydgard
0a844ce98d Delete functions for vsge and vslt, these have been rolled into VecDo3 2013-11-09 19:29:52 +01:00
Henrik Rydgard
63334698e1 Add temporary setting to disable the vertex decoder jit while we debug it 2013-11-09 18:16:26 +01:00
Unknown W. Brackets
a3a061a69f armjit: Optimize a division by a power of two. 
These really happen.
 2013-11-09 08:43:53 -08:00
Unknown W. Brackets
1776c85882 armjit: Implement a software divide for divu. 
It's not actually that much code.
 2013-11-09 08:43:52 -08:00
Unknown W. Brackets
b2a240d105 armjit: Implement msub/msubu. 2013-11-09 08:43:52 -08:00
Unknown W. Brackets
3aa8706ae7 armjit: Optimize lwl/lwr against an imm address. 2013-11-09 08:43:48 -08:00
Unknown W. Brackets
4026944b02 armjit: Handle lwl/lwr (not pretty, though.) 2013-11-09 08:42:30 -08:00
Henrik Rydgård
e90f7f360d Merge pull request #4480 from unknownbrackets/perf 
Flush regs using STMIA if possible, plus imm adjustments (armjit)
 2013-11-09 08:41:25 -08:00
Henrik Rydgard
06ce01ea04 Remove erroneous comment. 2013-11-09 17:34:52 +01:00
Unknown W. Brackets
54168b173e armjit: Clean up some magic numbers. 2013-11-09 08:25:08 -08:00
Unknown W. Brackets
6038d96b46 armjit: Flush regs using STMIA where possible. 2013-11-09 08:25:07 -08:00
Unknown W. Brackets
e686ff59bf armjit: Allocate regs in preferred slots. 
This may allow better flushing.  Not sure if these are the best regs,
but if they aren't it shouldn't really hurt.
 2013-11-09 08:25:07 -08:00
Unknown W. Brackets
cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00
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945b8bf5c5 armjit: optimize reverse subtract, avoid temp imms. 
If we have a non-op2 imm, get rid of it asap.  If we have a op2 friendly
imm, keep it.
 2013-11-09 08:18:43 -08:00
Unknown W. Brackets
415f22ecac armjit: Preserve imms on min/max as well. 2013-11-09 08:18:43 -08:00
Henrik Rydgard
502f772856 Add experimental mode to cache pointers in the arm jit. 
Turned off for now as it needs more work but seems quite promising already.
 2013-11-09 17:15:30 +01:00
Henrik Rydgard
58c39a38ee ARM regcache: Add mechanism to keep registers converted to pointers around 2013-11-09 16:57:29 +01:00
Henrik Rydgard
5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Henrik Rydgard
d26692ef92 Fix bug from a couple of commits ago in ARMJit 2013-11-09 15:22:39 +01:00
Henrik Rydgard
316d23d4cc Optimize mfv/mtv/mfc1/mtc1 on x86 too 2013-11-09 14:06:45 +01:00
Henrik Rydgard
04451623b9 This variant didn't seem to make much difference either (see prev commit) 2013-11-09 13:06:10 +01:00
Henrik Rydgard
15bc5a8db7 Add small ARM perf experiment. Did not help on ARMv7 so turned it off. 
xsacha might want to try it on ARMv6.
 2013-11-09 12:57:07 +01:00
Henrik Rydgard
2fe898cda8 Add comment with link to important github thread about sceSas threading 2013-11-09 02:05:28 +01:00
Unknown W. Brackets
5d46a82f43 armjit: Use a MOV for add/or with 0. 
Might skip the ALU, so might be faster.
 2013-11-08 11:41:57 -08:00
Unknown W. Brackets
b8e126e7ce armjit: Preserve imms in slt/sltu as possible. 2013-11-08 11:41:57 -08:00
Unknown W. Brackets
8393d4aaae armjit: Preserve immediates more in nor. 2013-11-08 11:41:56 -08:00
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d7e42b26a3 armjit: Avoid flushing imm on add t0, imm, imm. 2013-11-08 11:41:56 -08:00
Unknown W. Brackets
a435c9dd13 armjit: Optimize movz/movn with immediates. 2013-11-08 11:41:55 -08:00