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armjit: Handle lwl/lwr (not pretty, though.)
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2 changed files with 114 additions and 64 deletions
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@ -91,7 +91,7 @@ namespace MIPSComp
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}
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}
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void Jit::SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg) {
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void Jit::SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg, bool reverse) {
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SetR0ToEffectiveAddress(rs, offset);
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// There are three valid ranges. Each one gets a bit.
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@ -123,7 +123,116 @@ namespace MIPSComp
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// If we left any bit set, the address is OK.
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SetCC(CC_AL);
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CMP(tempReg, 0);
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SetCC(CC_GT);
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SetCC(reverse ? CC_EQ : CC_GT);
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}
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void Jit::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
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CONDITIONAL_DISABLE;
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int offset = (signed short)(op & 0xFFFF);
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (!js.inDelaySlot) {
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// Optimisation: Combine to single unaligned load/store
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bool isLeft = (o == 34 || o == 42);
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MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Find a matching shift in opposite direction with opposite offset.
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if (nextOp == (isLeft ? (op.encoding + (4<<26) - 3)
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: (op.encoding - (4<<26) + 3)))
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{
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EatInstruction(nextOp);
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nextOp = MIPSOpcode(((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF)); //lw, sw
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Comp_ITypeMem(nextOp);
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return;
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}
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}
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u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
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bool doCheck = false;
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FixupBranch skip;
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if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
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u32 addr = iaddr & 0x3FFFFFFF;
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// Must be OK even if rs == rt since we have the value from imm already.
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gpr.MapReg(rt, load ? MAP_NOINIT | MAP_DIRTY : 0);
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MOVI2R(R0, addr);
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} else {
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_dbg_assert_msg_(JIT, !gpr.IsImm(rs), "Invalid immediate address? CPU bug?");
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load ? gpr.MapDirtyIn(rt, rs, false) : gpr.MapInIn(rt, rs);
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if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
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SetCCAndR0ForSafeAddress(rs, offset, R1, true);
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doCheck = true;
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} else {
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SetR0ToEffectiveAddress(rs, offset);
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}
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}
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if (doCheck) {
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skip = B();
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}
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// Need temp regs. TODO: Get from the regcache?
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if (load) {
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PUSH(1, R10);
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} else {
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PUSH(2, R9, R10);
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}
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// Here's our shift amount.
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AND(R1, R0, 3);
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LSL(R1, R1, 3);
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// Now align the address for the actual read.
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BIC(R0, R0, 3);
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switch (o) {
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case 34: // lwl
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MOVI2R(R10, 0x00ffffff);
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LDR(R0, R11, R0);
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AND(gpr.R(rt), gpr.R(rt), Operand2(R10, ST_LSR, R1));
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RSB(R1, R1, 24);
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, R1));
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break;
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case 38: // lwr
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MOVI2R(R10, 0xffffff00);
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LDR(R0, R11, R0);
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LSR(R0, R0, R1);
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RSB(R1, R1, 24);
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AND(gpr.R(rt), gpr.R(rt), Operand2(R10, ST_LSL, R1));
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ORR(gpr.R(rt), gpr.R(rt), R0);
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break;
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case 42: // swl
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MOVI2R(R10, 0xffffff00);
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LDR(R9, R11, R0);
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AND(R9, R9, Operand2(R10, ST_LSL, R1));
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RSB(R1, R1, 24);
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ORR(R9, R9, Operand2(gpr.R(rt), ST_LSR, R1));
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STR(R9, R11, R0);
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break;
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case 46: // swr
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MOVI2R(R10, 0x00ffffff);
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LDR(R9, R11, R0);
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RSB(R1, R1, 24);
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AND(R9, R9, Operand2(R10, ST_LSR, R1));
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RSB(R1, R1, 24);
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ORR(R9, R9, Operand2(gpr.R(rt), ST_LSL, R1));
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STR(R9, R11, R0);
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break;
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}
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if (load) {
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POP(1, R10);
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} else {
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POP(2, R9, R10);
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}
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if (doCheck) {
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SetJumpTarget(skip);
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}
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}
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void Jit::Comp_ITypeMem(MIPSOpcode op)
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@ -225,67 +334,7 @@ namespace MIPSComp
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load = true;
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case 42: //swl
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case 46: //swr
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if (!js.inDelaySlot) {
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// Optimisation: Combine to single unaligned load/store
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bool isLeft = (o == 34 || o == 42);
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MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Find a matching shift in opposite direction with opposite offset.
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if (nextOp == (isLeft ? (op.encoding + (4<<26) - 3)
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: (op.encoding - (4<<26) + 3)))
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{
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EatInstruction(nextOp);
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nextOp = MIPSOpcode(((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF)); //lw, sw
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Comp_ITypeMem(nextOp);
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return;
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}
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}
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DISABLE; // Disabled until crashes are resolved.
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if (g_Config.bFastMemory) {
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int shift;
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if (gpr.IsImm(rs)) {
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u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
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shift = (addr & 3) << 3;
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addr &= 0xfffffffc;
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load ? gpr.MapReg(rt, MAP_DIRTY) : gpr.MapReg(rt, 0);
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MOVI2R(R0, addr);
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} else {
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load ? gpr.MapDirtyIn(rt, rs, false) : gpr.MapInIn(rt, rs);
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shift = (offset & 3) << 3; // Should be addr. Difficult as we don't know it yet.
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offset &= 0xfffffffc;
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SetR0ToEffectiveAddress(rs, offset);
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}
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switch (o)
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{
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// Load
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case 34:
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AND(gpr.R(rt), gpr.R(rt), 0x00ffffff >> shift);
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LDR(R0, R11, R0);
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, 24 - shift));
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break;
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case 38:
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AND(gpr.R(rt), gpr.R(rt), 0xffffff00 << (24 - shift));
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LDR(R0, R11, R0);
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSR, shift));
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break;
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// Store
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case 42:
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LDR(R1, R11, R0);
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AND(R1, R1, 0xffffff00 << shift);
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ORR(R1, R1, Operand2(gpr.R(rt), ST_LSR, 24 - shift));
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STR(R1, R11, R0);
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break;
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case 46:
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LDR(R1, R11, R0);
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AND(R1, R1, 0x00ffffff >> (24 - shift));
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ORR(R1, R1, Operand2(gpr.R(rt), ST_LSL, shift));
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STR(R1, R11, R0);
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break;
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}
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} else {
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Comp_Generic(op);
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return;
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}
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Comp_ITypeMemLR(op, load);
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break;
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default:
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Comp_Generic(op);
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@ -182,7 +182,8 @@ private:
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// Utils
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void SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset);
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void SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg);
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void SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg, bool reverse = false);
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void Comp_ITypeMemLR(MIPSOpcode op, bool load);
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JitBlockCache blocks;
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ArmJitOptions jo;
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