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775 commits

Author SHA1 Message Date
Henrik Rydgard
44e4ba8772 Merge branch 'master' into armjit-fpu 2013-02-15 21:42:44 +01:00
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e42e7bf22e Don't flush all regs in mfvc, just prefixes. 2013-02-15 09:50:07 -08:00
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f95e66eb98 Forget cached prefixes when calling generic. 
It may eat them, or maybe always does?
 2013-02-15 08:35:34 -08:00
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2b441f1638 Initial implementation of jit vadd/vsub/vdiv/vmul. 2013-02-15 08:35:34 -08:00
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b9506c9568 Minor cleanup for vdot in x86 jit. 2013-02-15 08:35:34 -08:00
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ccad259ae5 Keep track of VFPU prefixes and flush them in jit. 2013-02-15 08:35:33 -08:00
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f6f2927526 Add curlies around DISABLE/CONDITIONAL_DISABLE. 2013-02-15 08:35:33 -08:00
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4eca76e0cc Check for s/t/d prefix reg changes in jit. 2013-02-14 00:27:09 -08:00
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3b58cc27bd Oops, vfpu was missing CONDITIONAL_DISABLEs. 2013-02-14 00:27:09 -08:00
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abe390e6f3 Add some checks for fpu/vfpu writing to $0. 2013-02-14 00:27:09 -08:00
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4789a8e5eb Oops, can't have CONDITIONAL_DISABLE here, no op. 2013-02-14 00:27:08 -08:00
Henrik Rydgard
30318a4a4d Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/x86/CompFPU.cpp
 2013-02-13 20:47:41 +01:00
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f1386dfca1 Add a quick optimization to the x86 fpu comps. 2013-02-13 02:21:26 -08:00
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19cc652a37 Correct NaN handling in fpu comparisons. 2013-02-13 01:54:07 -08:00
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3cab6986c5 Jit the FPU comparisons on x86. 
Probably not too fast.  Also, NaN handling seems wrong?
 2013-02-13 00:55:10 -08:00
Henrik Rydgard
2c01b36585 Some FPU optimization 2013-02-12 00:58:31 +01:00
Henrik Rydgard
4eb89e6aec Merge branch 'master' into armjit-fpu 2013-02-11 19:22:14 +01:00
Henrik Rydgard
3ce4a8a719 Allow switching 2xSSAA on and off ingame. Add Show FPS menu option. 2013-02-11 19:02:38 +01:00
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7c428bfeba Fix immediate div CMP. 2013-02-10 10:02:55 -08:00
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e0ebfd2211 Jit div/divu in x86. 2013-02-10 09:36:41 -08:00
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9bb78ce2ec Jit madd/msub in x86. 2013-02-10 08:45:35 -08:00
Henrik Rydgard
3a11b030d6 Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/ARM/ArmCompFPU.cpp
	Core/MIPS/x86/CompFPU.cpp
 2013-02-10 15:57:16 +01:00
Henrik Rydgard
f75d14d3b5 ARM FPU jit work 2013-02-10 15:53:56 +01:00
Henrik Rydgard
78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
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eb84c2f00a Validate jumps in jit slowmem mode. 
This makes it easier to see what is going on in the emulator debugger.
 2013-02-09 23:11:26 -08:00
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71c85ccf33 In jit slowmem, verify actual address. 
Oops, it could crash if it was near the boundary.
Well, it still could if it were very near, but that's rare.
 2013-02-09 23:08:57 -08:00
Henrik Rydgard
377c94b125 JIT x86: cvt.s.w 2013-02-06 20:29:49 +01:00
Lewis Robbins
442e64cd84 compiler warning and const top-level const 2013-02-05 17:54:29 +00:00
lioncash
025a1351b4 Get rid of unused iterators. 
Also fix the formatting in 3 sprintf calls.
 2013-02-04 08:49:58 -05:00
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6bee870ac9 Fix CompShiftVar for x86 jit. 
In case rd == rs, need to load ECX first.  I can't find anything
else wrong with it for it to be disabled.
 2013-02-02 14:02:07 -08:00
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f777c872e6 Jit unaligned reads/writes. 
This mostly just improves perf on debug, not really on the map for release.
 2013-02-02 13:12:34 -08:00
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bab7947be6 Read delay slots as instructions not mem. 
Just in case - could be a jump target, maybe?  Never seen it, though.
 2013-02-02 11:46:35 -08:00
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44b5adeaac Properly jit the break instruction. 
Otherwise, it just keeps on going past it.
We never want to hit this anyway, but it's good to know if we do.
 2013-02-01 00:49:14 -08:00
Henrik Rydgard
c97f63a9d9 Minor armjit opt 2013-01-30 20:01:42 +01:00
Henrik Rydgard
90b11bba37 Implement mult, multu, mflo/hi, mtlo/hi in x86 JIT 2013-01-29 00:48:42 +01:00
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6d7a8d9b1a Apply the memview mask to jit immediates too. 2013-01-26 23:54:43 -08:00
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a7b5433ba7 Make sure fastmem isn't confused by rs changing. 2013-01-26 23:18:50 -08:00
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a89d61463e Make the VFPU jit use far jumps for memory access. 2013-01-26 23:08:19 -08:00
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0e8e9697c5 Add lv.q/sv.q support to the x86 jit. 2013-01-26 10:09:18 -08:00
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b77ce99d01 Oops, no slow read for immediates usually. 2013-01-26 09:27:52 -08:00
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9cd5836b85 Rename WriteFinish() to Finish() is safe mem. 
It's nothing to do with writing.
 2013-01-26 09:09:47 -08:00
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3e419f513a Refactor jit safe memory reads without dup code. 
But, maybe too automagical...
 2013-01-26 08:42:34 -08:00
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b7ef3e7bef Make sure to log / check bad immediate mem access. 
Although, theoretically, this should never happen.
Also, definitely time to refactor.
 2013-01-25 23:06:43 -08:00
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3418383917 Immediately break on bad mem access in jit slowmem. 2013-01-25 22:52:51 -08:00
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db5fa233a8 Make sure we don't mark a reg dirty on noop. 2013-01-25 22:34:01 -08:00
Henrik Rydgard
2738417040 VFPU JIT: start setting up infrastructure. very incomplete. vdot works if undisabled, but isn't complete. 2013-01-26 01:34:19 +01:00
Henrik Rydgard
68991511ee Split out the FPU reg cache into its own file too. 2013-01-26 01:34:19 +01:00
Henrik Rydgard
ad5e2b58c6 Separate the two regcaches before doing major surgery to FPURegCache. 2013-01-26 01:34:18 +01:00
Henrik Rydgard
dd149a50a3 Must flush FPR regcache before thrashing the fp regs 2013-01-25 19:55:30 +01:00
Henrik Rydgard
aabc0aa9ef Quick implementation of LV.Q and SV.Q in x86/x64 JIT 2013-01-25 19:50:30 +01:00