mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
Separate the two regcaches before doing major surgery to FPURegCache.
This commit is contained in:
Henrik Rydgard
parent
be12d2efe3
commit
ad5e2b58c6
2 changed files with 267 additions and 215 deletions
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@ -38,30 +38,22 @@ static const int allocationOrder[] =
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#endif
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};
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RegCache::RegCache() : emit(0), mips(0) {
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memset(locks, 0, sizeof(locks));
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memset(xlocks, 0, sizeof(xlocks));
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memset(saved_locks, 0, sizeof(saved_locks));
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memset(saved_xlocks, 0, sizeof(saved_xlocks));
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GPRRegCache::GPRRegCache() : emit(0), mips(0) {
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memset(regs, 0, sizeof(regs));
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memset(xregs, 0, sizeof(xregs));
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memset(saved_regs, 0, sizeof(saved_regs));
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memset(saved_xregs, 0, sizeof(saved_xregs));
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}
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void RegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats)
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{
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void GPRRegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
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this->mips = mips;
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for (int i = 0; i < NUMXREGS; i++)
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{
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for (int i = 0; i < NUM_X_REGS; i++) {
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xregs[i].free = true;
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xregs[i].dirty = false;
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xlocks[i] = false;
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xregs[i].allocLocked = false;
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}
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for (int i = 0; i < 32; i++)
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{
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for (int i = 0; i < NUM_MIPS_GPRS; i++) {
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regs[i].location = GetDefaultLocation(i);
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regs[i].away = false;
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regs[i].locked = false;
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}
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// todo: sort to find the most popular regs
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@ -81,66 +73,58 @@ void RegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats)
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//But only preload IF written OR reads >= 3
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}
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// these are MIPS reg indices
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void RegCache::Lock(int p1, int p2, int p3, int p4)
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{
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locks[p1] = true;
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if (p2 != 0xFF) locks[p2] = true;
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if (p3 != 0xFF) locks[p3] = true;
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if (p4 != 0xFF) locks[p4] = true;
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void GPRRegCache::Lock(int p1, int p2, int p3, int p4) {
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regs[p1].locked = true;
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if (p2 != 0xFF) regs[p2].locked = true;
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if (p3 != 0xFF) regs[p3].locked = true;
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if (p4 != 0xFF) regs[p4].locked = true;
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}
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// these are x64 reg indices
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void RegCache::LockX(int x1, int x2, int x3, int x4)
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{
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if (xlocks[x1]) {
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void GPRRegCache::LockX(int x1, int x2, int x3, int x4) {
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if (xregs[x1].allocLocked) {
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PanicAlert("RegCache: x %i already locked!", x1);
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}
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xlocks[x1] = true;
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if (x2 != 0xFF) xlocks[x2] = true;
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if (x3 != 0xFF) xlocks[x3] = true;
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if (x4 != 0xFF) xlocks[x4] = true;
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xregs[x1].allocLocked = true;
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if (x2 != 0xFF) xregs[x2].allocLocked = true;
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if (x3 != 0xFF) xregs[x3].allocLocked = true;
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if (x4 != 0xFF) xregs[x4].allocLocked = true;
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}
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bool RegCache::IsFreeX(int xreg) const
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{
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return xregs[xreg].free && !xlocks[xreg];
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}
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void RegCache::UnlockAll()
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{
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void GPRRegCache::UnlockAll() {
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for (int i = 0; i < 32; i++)
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locks[i] = false;
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regs[i].locked = false;
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}
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void RegCache::UnlockAllX()
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{
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for (int i = 0; i < NUMXREGS; i++)
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xlocks[i] = false;
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void GPRRegCache::UnlockAllX() {
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for (int i = 0; i < NUM_X_REGS; i++)
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xregs[i].allocLocked = false;
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}
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X64Reg RegCache::GetFreeXReg()
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X64Reg GPRRegCache::GetFreeXReg()
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{
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int aCount;
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const int *aOrder = GetAllocationOrder(aCount);
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for (int i = 0; i < aCount; i++)
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{
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X64Reg xr = (X64Reg)aOrder[i];
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if (!xlocks[xr] && xregs[xr].free)
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if (!xregs[xr].allocLocked && xregs[xr].free)
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{
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return (X64Reg)xr;
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}
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}
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//Okay, not found :( Force grab one
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//TODO - add a pass to grab xregs whose ppcreg is not used in the next 3 instructions
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//TODO - add a pass to grab xregs whose mipsreg is not used in the next 3 instructions
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for (int i = 0; i < aCount; i++)
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{
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X64Reg xr = (X64Reg)aOrder[i];
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if (xlocks[xr])
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if (xregs[xr].allocLocked)
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continue;
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int preg = xregs[xr].mipsReg;
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if (!locks[preg])
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if (!regs[preg].locked)
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{
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StoreFromRegister(preg);
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return xr;
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@ -151,39 +135,20 @@ X64Reg RegCache::GetFreeXReg()
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return (X64Reg) -1;
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}
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void RegCache::SaveState()
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void GPRRegCache::FlushR(X64Reg reg)
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{
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memcpy(saved_locks, locks, sizeof(locks));
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memcpy(saved_xlocks, xlocks, sizeof(xlocks));
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memcpy(saved_regs, regs, sizeof(regs));
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memcpy(saved_xregs, xregs, sizeof(xregs));
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}
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void RegCache::LoadState()
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{
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memcpy(xlocks, saved_xlocks, sizeof(xlocks));
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memcpy(locks, saved_locks, sizeof(locks));
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memcpy(regs, saved_regs, sizeof(regs));
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memcpy(xregs, saved_xregs, sizeof(xregs));
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}
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void RegCache::FlushR(X64Reg reg)
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{
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if (reg >= NUMXREGS)
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if (reg >= NUM_X_REGS)
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PanicAlert("Flushing non existent reg");
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if (!xregs[reg].free)
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{
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StoreFromRegister(xregs[reg].mipsReg);
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}
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}
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int RegCache::SanityCheck() const
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{
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int GPRRegCache::SanityCheck() const {
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for (int i = 0; i < 32; i++) {
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if (regs[i].away) {
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if (regs[i].location.IsSimpleReg()) {
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Gen::X64Reg simple = regs[i].location.GetSimpleReg();
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if (xlocks[simple])
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if (xregs[simple].allocLocked)
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return 1;
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if (xregs[simple].mipsReg != i)
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return 2;
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@ -195,10 +160,8 @@ int RegCache::SanityCheck() const
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return 0;
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}
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void RegCache::DiscardRegContentsIfCached(int preg)
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{
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if (regs[preg].away && regs[preg].location.IsSimpleReg())
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{
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void GPRRegCache::DiscardRegContentsIfCached(int preg) {
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if (regs[preg].away && regs[preg].location.IsSimpleReg()) {
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X64Reg xr = regs[preg].location.GetSimpleReg();
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xregs[xr].free = true;
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xregs[xr].dirty = false;
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@ -209,8 +172,7 @@ void RegCache::DiscardRegContentsIfCached(int preg)
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}
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void GPRRegCache::SetImmediate32(int preg, u32 immValue)
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{
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void GPRRegCache::SetImmediate32(int preg, u32 immValue) {
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// ZERO is always zero. Let's just make sure.
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if (preg == 0)
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immValue = 0;
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@ -220,16 +182,14 @@ void GPRRegCache::SetImmediate32(int preg, u32 immValue)
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regs[preg].location = Imm32(immValue);
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}
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bool GPRRegCache::IsImmediate(int preg) const
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{
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bool GPRRegCache::IsImmediate(int preg) const {
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// Always say yes for ZERO, even if it's in a temp reg.
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if (preg == 0)
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return true;
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return regs[preg].location.IsImm();
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}
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u32 GPRRegCache::GetImmediate32(int preg) const
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{
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u32 GPRRegCache::GetImmediate32(int preg) const {
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_dbg_assert_msg_(JIT, IsImmediate(preg), "Reg %d must be an immediate.", preg);
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// Always 0 for ZERO.
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if (preg == 0)
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@ -237,50 +197,19 @@ u32 GPRRegCache::GetImmediate32(int preg) const
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return regs[preg].location.GetImmValue();
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}
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void GPRRegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats)
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{
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RegCache::Start(mips, stats);
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}
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void FPURegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats)
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{
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RegCache::Start(mips, stats);
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}
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const int *GPRRegCache::GetAllocationOrder(int &count)
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{
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const int *GPRRegCache::GetAllocationOrder(int &count) {
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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}
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const int *FPURegCache::GetAllocationOrder(int &count)
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{
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static const int allocationOrder[] =
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{
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#ifdef _M_X64
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XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5
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#elif _M_IX86
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XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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#endif
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};
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count = sizeof(allocationOrder) / sizeof(int);
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return allocationOrder;
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}
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OpArg GPRRegCache::GetDefaultLocation(int reg) const
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{
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OpArg GPRRegCache::GetDefaultLocation(int reg) const {
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return M(&mips->r[reg]);
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}
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OpArg FPURegCache::GetDefaultLocation(int reg) const
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{
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return M(&mips->f[reg]);
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}
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void RegCache::KillImmediate(int preg, bool doLoad, bool makeDirty)
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{
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if (regs[preg].away)
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{
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void GPRRegCache::KillImmediate(int preg, bool doLoad, bool makeDirty) {
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if (regs[preg].away) {
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if (regs[preg].location.IsImm())
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BindToRegister(preg, doLoad, makeDirty);
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else if (regs[preg].location.IsSimpleReg())
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@ -288,65 +217,53 @@ void RegCache::KillImmediate(int preg, bool doLoad, bool makeDirty)
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}
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}
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void GPRRegCache::BindToRegister(int i, bool doLoad, bool makeDirty)
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{
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void GPRRegCache::BindToRegister(int i, bool doLoad, bool makeDirty) {
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if (!regs[i].away && regs[i].location.IsImm())
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PanicAlert("Bad immediate");
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if (!regs[i].away || (regs[i].away && regs[i].location.IsImm()))
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{
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if (!regs[i].away || (regs[i].away && regs[i].location.IsImm())) {
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X64Reg xr = GetFreeXReg();
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if (xregs[xr].dirty) PanicAlert("Xreg already dirty");
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if (xlocks[xr]) PanicAlert("GetFreeXReg returned locked register");
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if (xregs[xr].allocLocked) PanicAlert("GetFreeXReg returned locked register");
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xregs[xr].free = false;
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xregs[xr].mipsReg = i;
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xregs[xr].dirty = makeDirty || regs[i].location.IsImm();
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OpArg newloc = ::Gen::R(xr);
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if (doLoad)
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{
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if (doLoad) {
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// Force ZERO to be 0.
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if (i == 0)
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emit->MOV(32, newloc, Imm32(0));
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else
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emit->MOV(32, newloc, regs[i].location);
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}
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for (int j = 0; j < 32; j++)
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{
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if (i != j && regs[j].location.IsSimpleReg() && regs[j].location.GetSimpleReg() == xr)
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{
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for (int j = 0; j < 32; j++) {
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if (i != j && regs[j].location.IsSimpleReg() && regs[j].location.GetSimpleReg() == xr) {
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ERROR_LOG(JIT, "BindToRegister: Strange condition");
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Crash();
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}
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}
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regs[i].away = true;
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regs[i].location = newloc;
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}
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else
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{
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} else {
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// reg location must be simplereg; memory locations
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// and immediates are taken care of above.
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xregs[RX(i)].dirty |= makeDirty;
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}
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if (xlocks[RX(i)]) {
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if (xregs[RX(i)].allocLocked) {
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PanicAlert("Seriously WTF, this reg should have been flushed");
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}
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}
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void GPRRegCache::StoreFromRegister(int i)
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{
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if (regs[i].away)
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{
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void GPRRegCache::StoreFromRegister(int i) {
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if (regs[i].away) {
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bool doStore;
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if (regs[i].location.IsSimpleReg())
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{
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if (regs[i].location.IsSimpleReg()) {
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X64Reg xr = RX(i);
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xregs[xr].free = true;
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xregs[xr].mipsReg = -1;
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doStore = xregs[xr].dirty;
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xregs[xr].dirty = false;
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}
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else
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{
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} else {
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//must be immediate - do nothing
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doStore = true;
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}
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@ -359,14 +276,73 @@ void GPRRegCache::StoreFromRegister(int i)
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}
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}
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void FPURegCache::BindToRegister(int i, bool doLoad, bool makeDirty)
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void GPRRegCache::Flush(FlushMode mode)
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{
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for (int i = 0; i < NUM_X_REGS; i++) {
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if (xregs[i].allocLocked)
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PanicAlert("Someone forgot to unlock X64 reg %i.", i);
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}
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for (int i = 0; i < 32; i++) {
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if (regs[i].locked) {
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PanicAlert("Somebody forgot to unlock MIPS reg %i.", i);
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}
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if (regs[i].away) {
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if (regs[i].location.IsSimpleReg()) {
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X64Reg xr = RX(i);
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StoreFromRegister(i);
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xregs[xr].dirty = false;
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}
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else if (regs[i].location.IsImm()) {
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StoreFromRegister(i);
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} else {
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_assert_msg_(DYNA_REC,0,"Jit64 - Flush unhandled case, reg %i PC: %08x", i, mips->pc);
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}
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}
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}
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}
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FPURegCache::FPURegCache() : emit(0), mips(0) {
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memset(regs, 0, sizeof(regs));
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memset(xregs, 0, sizeof(xregs));
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}
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void FPURegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
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this->mips = mips;
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for (int i = 0; i < NUM_X_REGS; i++) {
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xregs[i].free = true;
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xregs[i].dirty = false;
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xregs[i].allocLocked = false;
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}
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for (int i = 0; i < 32; i++) {
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regs[i].location = GetDefaultLocation(i);
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regs[i].away = false;
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regs[i].locked = false;
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}
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}
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void FPURegCache::Lock(int p1, int p2, int p3, int p4) {
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regs[p1].locked = true;
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if (p2 != 0xFF) regs[p2].locked = true;
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if (p3 != 0xFF) regs[p3].locked = true;
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if (p4 != 0xFF) regs[p4].locked = true;
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}
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void FPURegCache::UnlockAll() {
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for (int i = 0; i < 32; i++)
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regs[i].locked = false;
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}
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void FPURegCache::UnlockAllX() {
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for (int i = 0; i < NUM_X_REGS; i++)
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xregs[i].allocLocked = false;
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}
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void FPURegCache::BindToRegister(int i, bool doLoad, bool makeDirty) {
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_assert_msg_(DYNA_REC, !regs[i].location.IsImm(), "WTF - load - imm");
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if (!regs[i].away)
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{
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if (!regs[i].away) {
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// Reg is at home in the memory register file. Let's pull it out.
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X64Reg xr = GetFreeXReg();
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_assert_msg_(DYNA_REC, xr < NUMXREGS, "WTF - load - invalid reg");
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_assert_msg_(DYNA_REC, xr < NUM_X_REGS, "WTF - load - invalid reg");
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xregs[xr].mipsReg = i;
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xregs[xr].free = false;
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xregs[xr].dirty = makeDirty;
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@ -387,13 +363,11 @@ void FPURegCache::BindToRegister(int i, bool doLoad, bool makeDirty)
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}
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}
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void FPURegCache::StoreFromRegister(int i)
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{
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void FPURegCache::StoreFromRegister(int i) {
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_assert_msg_(DYNA_REC, !regs[i].location.IsImm(), "WTF - store - imm");
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if (regs[i].away)
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{
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if (regs[i].away) {
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X64Reg xr = regs[i].location.GetSimpleReg();
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_assert_msg_(DYNA_REC, xr < NUMXREGS, "WTF - store - invalid reg");
|
||||
_assert_msg_(DYNA_REC, xr < NUM_X_REGS, "WTF - store - invalid reg");
|
||||
xregs[xr].free = true;
|
||||
xregs[xr].dirty = false;
|
||||
xregs[xr].mipsReg = -1;
|
||||
|
|
@ -401,41 +375,98 @@ void FPURegCache::StoreFromRegister(int i)
|
|||
emit->MOVSS(newLoc, xr);
|
||||
regs[i].location = newLoc;
|
||||
regs[i].away = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
// _assert_msg_(DYNA_REC,0,"already stored");
|
||||
}
|
||||
}
|
||||
|
||||
void RegCache::Flush(FlushMode mode)
|
||||
{
|
||||
for (int i = 0; i < NUMXREGS; i++) {
|
||||
if (xlocks[i])
|
||||
void FPURegCache::Flush(FlushMode mode) {
|
||||
for (int i = 0; i < NUM_X_REGS; i++) {
|
||||
if (xregs[i].allocLocked)
|
||||
PanicAlert("Someone forgot to unlock X64 reg %i.", i);
|
||||
}
|
||||
for (int i = 0; i < 32; i++)
|
||||
{
|
||||
if (locks[i])
|
||||
{
|
||||
PanicAlert("Somebody forgot to unlock PPC reg %i.", i);
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (regs[i].locked) {
|
||||
PanicAlert("Somebody forgot to unlock MIPS reg %i.", i);
|
||||
}
|
||||
if (regs[i].away)
|
||||
{
|
||||
if (regs[i].location.IsSimpleReg())
|
||||
{
|
||||
if (regs[i].away) {
|
||||
if (regs[i].location.IsSimpleReg()) {
|
||||
X64Reg xr = RX(i);
|
||||
StoreFromRegister(i);
|
||||
xregs[xr].dirty = false;
|
||||
}
|
||||
else if (regs[i].location.IsImm())
|
||||
{
|
||||
} else if (regs[i].location.IsImm()) {
|
||||
StoreFromRegister(i);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
_assert_msg_(DYNA_REC,0,"Jit64 - Flush unhandled case, reg %i PC: %08x", i, mips->pc);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
OpArg FPURegCache::GetDefaultLocation(int reg) const {
|
||||
return M(&mips->f[reg]);
|
||||
}
|
||||
|
||||
int FPURegCache::SanityCheck() const {
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (regs[i].away) {
|
||||
if (regs[i].location.IsSimpleReg()) {
|
||||
Gen::X64Reg simple = regs[i].location.GetSimpleReg();
|
||||
if (xregs[simple].allocLocked)
|
||||
return 1;
|
||||
if (xregs[simple].mipsReg != i)
|
||||
return 2;
|
||||
}
|
||||
else if (regs[i].location.IsImm())
|
||||
return 3;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
const int *FPURegCache::GetAllocationOrder(int &count) {
|
||||
static const int allocationOrder[] = {
|
||||
#ifdef _M_X64
|
||||
XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5
|
||||
#elif _M_IX86
|
||||
XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
||||
#endif
|
||||
};
|
||||
count = sizeof(allocationOrder) / sizeof(int);
|
||||
return allocationOrder;
|
||||
}
|
||||
|
||||
X64Reg FPURegCache::GetFreeXReg() {
|
||||
int aCount;
|
||||
const int *aOrder = GetAllocationOrder(aCount);
|
||||
for (int i = 0; i < aCount; i++) {
|
||||
X64Reg xr = (X64Reg)aOrder[i];
|
||||
if (!xregs[xr].allocLocked && xregs[xr].free) {
|
||||
return (X64Reg)xr;
|
||||
}
|
||||
}
|
||||
//Okay, not found :( Force grab one
|
||||
|
||||
//TODO - add a pass to grab xregs whose mipsreg is not used in the next 3 instructions
|
||||
for (int i = 0; i < aCount; i++) {
|
||||
X64Reg xr = (X64Reg)aOrder[i];
|
||||
if (xregs[xr].allocLocked)
|
||||
continue;
|
||||
int preg = xregs[xr].mipsReg;
|
||||
if (!regs[preg].locked) {
|
||||
StoreFromRegister(preg);
|
||||
return xr;
|
||||
}
|
||||
}
|
||||
//Still no dice? Die!
|
||||
_assert_msg_(DYNA_REC, 0, "Regcache ran out of regs");
|
||||
return (X64Reg) -1;
|
||||
}
|
||||
|
||||
void FPURegCache::FlushR(X64Reg reg) {
|
||||
if (reg >= NUM_X_REGS)
|
||||
PanicAlert("Flushing non existent reg");
|
||||
if (!xregs[reg].free) {
|
||||
StoreFromRegister(xregs[reg].mipsReg);
|
||||
}
|
||||
}
|
||||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include "x64Emitter.h"
|
||||
#include "../MIPSAnalyst.h"
|
||||
|
||||
using namespace Gen;
|
||||
enum FlushMode
|
||||
{
|
||||
|
|
@ -36,6 +37,7 @@ struct MIPSCachedReg
|
|||
{
|
||||
OpArg location;
|
||||
bool away; // value not in source register
|
||||
bool locked;
|
||||
};
|
||||
|
||||
struct X64CachedReg
|
||||
|
|
@ -43,48 +45,34 @@ struct X64CachedReg
|
|||
int mipsReg;
|
||||
bool dirty;
|
||||
bool free;
|
||||
bool allocLocked;
|
||||
};
|
||||
|
||||
typedef int XReg;
|
||||
typedef int PReg;
|
||||
|
||||
#ifdef _M_X64
|
||||
#define NUMXREGS 16
|
||||
#define NUM_X_REGS 16
|
||||
#elif _M_IX86
|
||||
#define NUMXREGS 8
|
||||
#define NUM_X_REGS 8
|
||||
#endif
|
||||
|
||||
class RegCache
|
||||
// TODO: Add more cachable regs, like HI, LO
|
||||
#define NUM_MIPS_GPRS 32
|
||||
#define NUM_MIPS_FPRS 32
|
||||
|
||||
class GPRRegCache
|
||||
{
|
||||
private:
|
||||
bool locks[32];
|
||||
bool saved_locks[32];
|
||||
bool saved_xlocks[NUMXREGS];
|
||||
|
||||
protected:
|
||||
bool xlocks[NUMXREGS];
|
||||
MIPSCachedReg regs[32];
|
||||
X64CachedReg xregs[NUMXREGS];
|
||||
|
||||
MIPSCachedReg saved_regs[32];
|
||||
X64CachedReg saved_xregs[NUMXREGS];
|
||||
|
||||
virtual const int *GetAllocationOrder(int &count) = 0;
|
||||
|
||||
XEmitter *emit;
|
||||
|
||||
public:
|
||||
MIPSState *mips;
|
||||
RegCache();
|
||||
|
||||
virtual ~RegCache() {}
|
||||
virtual void Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) = 0;
|
||||
GPRRegCache();
|
||||
~GPRRegCache() {}
|
||||
void Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats);
|
||||
|
||||
void DiscardRegContentsIfCached(int preg);
|
||||
void SetEmitter(XEmitter *emitter) {emit = emitter;}
|
||||
|
||||
void FlushR(X64Reg reg);
|
||||
void FlushR(X64Reg reg, X64Reg reg2) {FlushR(reg); FlushR(reg2);}
|
||||
void FlushLockX(X64Reg reg) {
|
||||
FlushR(reg);
|
||||
LockX(reg);
|
||||
|
|
@ -93,15 +81,12 @@ public:
|
|||
FlushR(reg1); FlushR(reg2);
|
||||
LockX(reg1); LockX(reg2);
|
||||
}
|
||||
virtual void Flush(FlushMode mode);
|
||||
// virtual void Flush(PPCAnalyst::CodeOp *op) {Flush(FLUSH_ALL);}
|
||||
void Flush(FlushMode mode);
|
||||
int SanityCheck() const;
|
||||
void KillImmediate(int preg, bool doLoad, bool makeDirty);
|
||||
|
||||
//TODO - instead of doload, use "read", "write"
|
||||
//read only will not set dirty flag
|
||||
virtual void BindToRegister(int preg, bool doLoad = true, bool makeDirty = true) = 0;
|
||||
virtual void StoreFromRegister(int preg) = 0;
|
||||
void BindToRegister(int preg, bool doLoad = true, bool makeDirty = true);
|
||||
void StoreFromRegister(int preg);
|
||||
|
||||
const OpArg &R(int preg) const {return regs[preg].location;}
|
||||
X64Reg RX(int preg) const
|
||||
|
|
@ -111,7 +96,7 @@ public:
|
|||
PanicAlert("Not so simple - %i", preg);
|
||||
return (X64Reg)-1;
|
||||
}
|
||||
virtual OpArg GetDefaultLocation(int reg) const = 0;
|
||||
OpArg GetDefaultLocation(int reg) const;
|
||||
|
||||
// Register locking.
|
||||
void Lock(int p1, int p2=0xff, int p3=0xff, int p4=0xff);
|
||||
|
|
@ -119,34 +104,70 @@ public:
|
|||
void UnlockAll();
|
||||
void UnlockAllX();
|
||||
|
||||
bool IsFreeX(int xreg) const;
|
||||
|
||||
X64Reg GetFreeXReg();
|
||||
|
||||
void SaveState();
|
||||
void LoadState();
|
||||
};
|
||||
|
||||
class GPRRegCache : public RegCache
|
||||
{
|
||||
public:
|
||||
void Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats);
|
||||
void BindToRegister(int preg, bool doLoad = true, bool makeDirty = true);
|
||||
void StoreFromRegister(int preg);
|
||||
OpArg GetDefaultLocation(int reg) const;
|
||||
const int *GetAllocationOrder(int &count);
|
||||
void SetImmediate32(int preg, u32 immValue);
|
||||
bool IsImmediate(int preg) const;
|
||||
u32 GetImmediate32(int preg) const;
|
||||
|
||||
private:
|
||||
MIPSCachedReg regs[NUM_MIPS_GPRS];
|
||||
X64CachedReg xregs[NUM_X_REGS];
|
||||
|
||||
const int *GetAllocationOrder(int &count);
|
||||
|
||||
XEmitter *emit;
|
||||
};
|
||||
|
||||
|
||||
class FPURegCache : public RegCache
|
||||
// Now also with VFPU support!
|
||||
class FPURegCache
|
||||
{
|
||||
public:
|
||||
MIPSState *mips;
|
||||
FPURegCache();
|
||||
~FPURegCache() {}
|
||||
|
||||
void Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats);
|
||||
void BindToRegister(int preg, bool doLoad = true, bool makeDirty = true);
|
||||
void StoreFromRegister(int preg);
|
||||
const int *GetAllocationOrder(int &count);
|
||||
OpArg GetDefaultLocation(int reg) const;
|
||||
|
||||
void SetEmitter(XEmitter *emitter) {emit = emitter;}
|
||||
|
||||
void FlushLockX(X64Reg reg) {
|
||||
FlushR(reg);
|
||||
LockX(reg);
|
||||
}
|
||||
void FlushLockX(X64Reg reg1, X64Reg reg2) {
|
||||
FlushR(reg1); FlushR(reg2);
|
||||
LockX(reg1); LockX(reg2);
|
||||
}
|
||||
void Flush(FlushMode mode);
|
||||
int SanityCheck() const;
|
||||
|
||||
const OpArg &R(int preg) const {return regs[preg].location;}
|
||||
X64Reg RX(int preg) const
|
||||
{
|
||||
if (regs[preg].away && regs[preg].location.IsSimpleReg())
|
||||
return regs[preg].location.GetSimpleReg();
|
||||
PanicAlert("Not so simple - %i", preg);
|
||||
return (X64Reg)-1;
|
||||
}
|
||||
|
||||
// Register locking. Prevents them from being spilled.
|
||||
void Lock(int p1, int p2=0xff, int p3=0xff, int p4=0xff);
|
||||
void LockX(int x1, int x2=0xff, int x3=0xff, int x4=0xff);
|
||||
void UnlockAll();
|
||||
void UnlockAllX();
|
||||
|
||||
private:
|
||||
X64Reg GetFreeXReg();
|
||||
void FlushR(X64Reg reg);
|
||||
const int *GetAllocationOrder(int &count);
|
||||
|
||||
MIPSCachedReg regs[NUM_MIPS_FPRS];
|
||||
X64CachedReg xregs[NUM_X_REGS];
|
||||
|
||||
XEmitter *emit;
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue