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Properly jit the break instruction.

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Otherwise, it just keeps on going past it.
We never want to hit this anyway, but it's good to know if we do.
This commit is contained in:
Unknown W. Brackets 2013-02-01 00:49:14 -08:00
parent ec8f080491
commit 44b5adeaac
6 changed files with 18 additions and 2 deletions
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7
Core/MIPS/ARM/ArmCompBranch.cpp
View file

@ -422,4 +422,11 @@ void Jit::Comp_Syscall(u32 op)
js.compiling = false;
}
void Jit::Comp_Break(u32 op)
{
Comp_Generic(op);
WriteSyscallExit();
js.compiling = false;
}
} // namespace Mipscomp

1
Core/MIPS/ARM/ArmJit.h
View file

@ -89,6 +89,7 @@ public:
void Comp_Jump(u32 op);
void Comp_JumpReg(u32 op);
void Comp_Syscall(u32 op);
void Comp_Break(u32 op);
void Comp_IType(u32 op);
void Comp_RType3(u32 op);

2
Core/MIPS/MIPSInt.cpp
View file

@ -179,7 +179,7 @@ namespace MIPSInt
void Int_Break(u32 op)
{
DEBUG_LOG(CPU, "BREAK!");
ERROR_LOG(CPU, "BREAK!");
coreState = CORE_STEPPING;
PC += 4;
}

2
Core/MIPS/MIPSTables.cpp
View file

@ -183,7 +183,7 @@ const MIPSInstruction tableSpecial[64] = /// 000000 ...... ...... .......... xxx
INSTR("movz", &Jit::Comp_RType3, Dis_RType3, Int_RType3, OUT_RD|IN_RS|IN_RT),
INSTR("movn", &Jit::Comp_RType3, Dis_RType3, Int_RType3, OUT_RD|IN_RS|IN_RT),
INSTR("syscall", &Jit::Comp_Syscall, Dis_Syscall, Int_Syscall,0),
INSTR("break", &Jit::Comp_Generic, Dis_Generic, Int_Break, 0),
INSTR("break", &Jit::Comp_Break, Dis_Generic, Int_Break, 0),
{-2},
INSTR("sync", &Jit::Comp_Generic, Dis_Generic, Int_Sync, 0),

7
Core/MIPS/x86/CompBranch.cpp
View file

@ -506,4 +506,11 @@ void Jit::Comp_Syscall(u32 op)
js.compiling = false;
}
void Jit::Comp_Break(u32 op)
{
Comp_Generic(op);
WriteSyscallExit();
js.compiling = false;
}
} // namespace Mipscomp

1
Core/MIPS/x86/Jit.h
View file

@ -122,6 +122,7 @@ public:
void Comp_Jump(u32 op);
void Comp_JumpReg(u32 op);
void Comp_Syscall(u32 op);
void Comp_Break(u32 op);
void Comp_IType(u32 op);
void Comp_RType3(u32 op);