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Author SHA1 Message Date
Dillon Beliveau
01b5494f74 copy in previous res correctly 2021-01-03 21:59:12 -05:00
Dillon Beliveau
cb5bce814b vmov actually works fine 2021-01-03 21:49:07 -05:00
Dillon Beliveau
b0bf59e753 use random vs if instruction is marked as using it 2021-01-03 21:35:33 -05:00
Dillon Beliveau
b5d504bc2c field for if tests should have a random vs 2021-01-03 20:45:08 -05:00
Dillon Beliveau
b86eb37f59 display more information in rsp fuzzer 2021-01-03 20:36:16 -05:00
Dillon Beliveau
113ebb7114 cleanup VMOV 2021-01-03 20:34:53 -05:00
Dillon Beliveau
ec6fbecdb7 print out emu versions of res & accumulator 2021-01-03 19:46:13 -05:00
Dillon Beliveau
bf589dffe7 turn off LTO 2021-01-03 17:55:57 -05:00
Dillon Beliveau
613cbddb8a quiet down rsp fuzzer output 2021-01-03 17:55:04 -05:00
Dillon Beliveau
9046e0bc9e RSP fuzzer configurable number of fuzzes per instruction, init state from hardware, comment out broken instructions 2021-01-03 17:19:34 -05:00
Dillon Beliveau
41964fef04 vnop is just a nop 2021-01-03 16:44:09 -05:00
Dillon Beliveau
0c1260c874 vnor works with non-zero element 2021-01-03 16:29:45 -05:00
Dillon Beliveau
5412ffb89a vnand works with non-zero element 2021-01-03 16:24:45 -05:00
Dillon Beliveau
0e2030f039 comment out unimplemented instructions, remove unused function 2021-01-02 10:45:10 -05:00
Dillon Beliveau
c15003713a link against core 2021-01-02 10:26:50 -05:00
Dillon Beliveau
eef74b6e47 automatically test each instruction 1000 times 2021-01-02 10:26:07 -05:00
Dillon Beliveau
c7e87bb865 send instruction to test over the wire 2021-01-02 09:28:10 -05:00
Dillon Beliveau
b57138d22f fix VRSQ side effect 2020-12-31 17:57:28 -05:00
Dillon Beliveau
a99e2bcb70 colors in flag reg output 2020-12-31 16:54:28 -05:00
Dillon Beliveau
c61aa4a9cf compare flag regs 2020-12-31 16:47:02 -05:00
Dillon Beliveau
b9888e7a8f run infinite random tests from RSP fuzzer 2020-12-31 16:23:51 -05:00
Dillon Beliveau
4792e259e4 receive and verify flag registers 2020-12-31 16:13:05 -05:00
Dillon Beliveau
84425e17af RSP fuzzer compares accumulator as well 2020-12-31 14:34:52 -05:00
Dillon Beliveau
048df5ccbf first pass at an RSP fuzzer 2020-12-30 23:02:55 -05:00
Dillon Beliveau
b6c08bbe44 turn on LTO 2020-12-29 17:00:41 -05:00
Dillon Beliveau
17dc2b1f6e quiet! 2020-12-29 17:00:35 -05:00
Dillon Beliveau
0a11e8057f remove stray dep on dma.c/h 2020-12-29 14:54:43 -05:00
Dillon Beliveau
b8ade649cd fix PI_DRAM_ADDR alignment 2020-12-29 14:51:39 -05:00
Dillon Beliveau
185160c1fd get rid of dma.c/h 2020-12-29 14:37:28 -05:00
Dillon Beliveau
aefd7490fb 64 bit TLB, hopefully works 2020-12-29 13:57:01 -05:00
Dillon Beliveau
139ddfbebf tlb fixes, prep for 64 bit TLB 2020-12-29 02:32:50 -05:00
Dillon Beliveau
1f8fec6dec more 64 bit accesses, detect TLB operations in 64 bit mode 2020-12-28 19:50:26 -05:00
Dillon Beliveau
0c9783a73b ll, sc 2020-12-28 19:30:06 -05:00
Dillon Beliveau
5fae26ef7b XKPHYS 2020-12-28 19:25:14 -05:00
Dillon Beliveau
babd540ef9 SCD 2020-12-28 19:25:10 -05:00
Dillon Beliveau
0845fb6ef1 lld in interpreter 2020-12-28 18:37:49 -05:00
Dillon Beliveau
854805a585 ignore writes to cart_2_1 2020-12-28 18:24:06 -05:00
Dillon Beliveau
10238640e5 64 bit version of entry_hi 2020-12-28 18:23:54 -05:00
Dillon Beliveau
75ff5f2c64 allow reads from FCR0, with a warning 2020-12-28 18:11:16 -05:00
Dillon Beliveau
946e929506 tne in interpreter 2020-12-28 18:11:16 -05:00
Dillon Beliveau
f47948369e return 0 for word reads from cart 1_3 2020-12-28 18:11:16 -05:00
Dillon Beliveau
c124a3596b context and xcontext in 64 bit mode 2020-12-28 18:11:16 -05:00
Dillon Beliveau
05a0c81088 register size fixes 2020-12-28 18:11:16 -05:00
Dillon Beliveau
1344530614 CP0 registers docs updates 2020-12-28 18:11:16 -05:00
Dillon Beliveau
d4599c16d8
Merge pull request #7 from YetAnotherEmuDev/master 
Make readme more polite
 2020-12-28 15:23:06 -05:00
YetAnotherEmuDev
706d123f72
Make readme more polite 2020-12-28 20:18:26 +00:00
Dillon Beliveau
386ad69832
Merge pull request #6 from wheremyfoodat/patch-1 
Made readme more polite
 2020-12-28 15:13:52 -05:00
wheremyfoodat
2158559ddd
Made readme more polite 2020-12-28 22:11:51 +02:00
Dillon Beliveau
38947cbcb3 update some format strings for 64 bit addressing 2020-12-28 03:16:08 -05:00
Dillon Beliveau
8e47d4c784 latest version of parallel-rdp 2020-12-28 03:00:22 -05:00