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Author SHA1 Message Date
Dillon Beliveau
095ef736fc not sure why this was still here 2020-12-28 01:06:06 -05:00
Dillon Beliveau
a4304ddf36 c.un 2020-12-28 00:55:04 -05:00
Dillon Beliveau
2c25314dab fix MI_VERSION_REG 2020-12-28 00:53:59 -05:00
Dillon Beliveau
6b991b50ff probably incorrect c.ule 2020-12-28 00:32:05 -05:00
Dillon Beliveau
0a09de0365 daddiu doesn't throw overflow exceptions 2020-12-28 00:24:21 -05:00
Dillon Beliveau
8178bb7216 RDP command processing fixes 2020-12-28 00:15:56 -05:00
Dillon Beliveau
41d12a23f8 DMTC0/DMFC0 2020-12-27 17:11:37 -05:00
Dillon Beliveau
a858271685 don't crash on vsync of 0x20C 2020-12-27 12:59:38 -05:00
Dillon Beliveau
85e4fdfcad split into own method 2020-12-27 12:28:00 -05:00
Dillon Beliveau
df3b120235 mask DRAM address in SI DMA 2020-12-27 02:15:06 -05:00
Dillon Beliveau
31936ecc2a don't lower interrupts randomly 2020-12-27 02:14:57 -05:00
Dillon Beliveau
999562468c mask Count reg 2020-12-27 02:14:49 -05:00
Dillon Beliveau
24e9d8f6cc hack: write RDRAM size to 0x318 after first PI DMA 2020-12-27 02:14:28 -05:00
Dillon Beliveau
9ef2d59872 RI regs are writable, and are initialized to certain values 2020-12-27 02:08:33 -05:00
Dillon Beliveau
3cb763a164 TEQ in JIT 2020-12-27 01:36:36 -05:00
Dillon Beliveau
4b9224067c TEQ in interpreter 2020-12-27 01:18:16 -05:00
Dillon Beliveau
6a10e1c50a XKUSEG probe TLB 2020-12-26 23:18:20 -05:00
Dillon Beliveau
d69ab0cd32 64 bit addressing working 2020-12-26 23:15:03 -05:00
Dillon Beliveau
6e8bfa93fd frameworking out 64 bit addressing 2020-12-26 22:19:21 -05:00
Dillon Beliveau
b5c2b84261 NaN checks in FPU instructions 2020-12-26 19:36:17 -05:00
Dillon Beliveau
51f49b77f5 fix DIV when dividing by zero 2020-12-26 19:11:28 -05:00
Dillon Beliveau
5f7399bc7d log rom name 2020-12-26 18:35:42 -05:00
Dillon Beliveau
34fc64a2d5 CP0 fixes 2020-12-26 18:33:48 -05:00
Dillon Beliveau
4ca695c42f inc PI DRAM and CART addresses by the length 2020-12-26 17:03:52 -05:00
Dillon Beliveau
8d932033e9 set wired and context 2020-12-26 17:03:42 -05:00
Dillon Beliveau
6bedb31d1e write word to SRAM from 2_1 2020-12-26 17:01:11 -05:00
Dillon Beliveau
f6265bbee0 size asserts 2020-12-26 17:00:23 -05:00
Dillon Beliveau
e228958190 slower, but hopefully more accurate, RSP timing 2020-12-26 15:20:06 -05:00
Dillon Beliveau
13ed5844f8 tweaks and cleanup - macros 2020-12-26 15:19:54 -05:00
Dillon Beliveau
1331d482d5 support reading more PI DMA regs 2020-12-26 14:02:24 -05:00
Dillon Beliveau
a59eede65d latest version of parallel-rdp 2020-12-26 14:01:03 -05:00
Dillon Beliveau
e851332316 cleanup macros 2020-12-26 13:48:19 -05:00
Dillon Beliveau
a27a0cc9a4 faster srlv, mfhi, mthi, mflo, mtlo 2020-12-26 13:46:28 -05:00
Dillon Beliveau
0c00a8b0e4 sllv 2020-12-26 13:38:03 -05:00
Dillon Beliveau
9db558df63 faster srav 2020-12-26 13:32:23 -05:00
Dillon Beliveau
d6160bc298 just warn when byte read from N64DD 2020-12-25 23:52:08 -05:00
Dillon Beliveau
82c3791a66 RSP: sltiu, sltu 2020-12-25 22:57:19 -05:00
Dillon Beliveau
9bd908793b ldc1/sdc1/lwc1/swc1 exception handling in JIT 2020-12-25 22:43:51 -05:00
Dillon Beliveau
8cea5accbd check cp1 exceptions ldc1/sdc1/lwc1/swc1 2020-12-25 21:55:31 -05:00
Dillon Beliveau
7674bd1cac exception fixes/updates 2020-12-25 20:22:25 -05:00
Dillon Beliveau
e50539acef size assertions 2020-12-25 19:54:02 -05:00
Dillon Beliveau
b185ffa0f9 check FPU exceptions in CTC1 2020-12-25 19:13:06 -05:00
Dillon Beliveau
dfe2b2d8b8 GDB stub updates and fixes 2020-12-25 16:26:38 -05:00
Dillon Beliveau
861e04d5e6 allow switching between jit and interpreter without recompiling, debug mode forces interpreter 2020-12-25 14:43:21 -05:00
Dillon Beliveau
edc809993b don't queue audio if more than half a second is already queued 2020-12-24 18:11:33 -05:00
Dillon Beliveau
0f8a3e2ea0 write byte to SRAM in REGION_CART_2_2 2020-12-24 18:10:54 -05:00
Dillon Beliveau
348aad1777 RSP timing tweaks 2020-12-24 18:06:44 -05:00
Dillon Beliveau
f41cecd264 sram read from cart_2_1 2020-12-24 18:06:14 -05:00
Dillon Beliveau
d30a700930 update bus errors/warnings 2020-12-24 16:29:30 -05:00
Dillon Beliveau
80c5d7f076 SRAM 2020-12-24 16:25:10 -05:00