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Author SHA1 Message Date
Dillon Beliveau
89f5cc32fb cleanup a bit of code in dynarec 2020-12-24 00:31:15 -05:00
Dillon Beliveau
a77cc704c2 USR2 turns logging back off 2020-12-24 00:31:02 -05:00
Dillon Beliveau
087509f096 remove 2 log lines 2020-12-24 00:24:15 -05:00
Dillon Beliveau
5583d4fe22 turn on debug logging when USR1 signal received 2020-12-24 00:06:41 -05:00
Dillon Beliveau
e95ce62921 JIT: make branches to self take 64 cycles in the, macro some switch statements 2020-12-23 22:41:23 -05:00
Dillon Beliveau
2f28a24a2d TLB translations in KSEG3 2020-12-23 21:30:13 -05:00
Dillon Beliveau
3b0ca0a2e1 compile TLBR 2020-12-23 21:30:05 -05:00
Dillon Beliveau
a16a3bda73 LUI with no UB 2020-12-23 19:50:11 -05:00
Dillon Beliveau
608ec61486 only inc count in one place 2020-12-23 19:50:06 -05:00
Dillon Beliveau
16a34d43a5 sync up with new jit timings 2020-12-23 19:49:54 -05:00
Dillon Beliveau
d73b2643c3 return zero when outside of the cart range 2020-12-23 19:15:45 -05:00
Dillon Beliveau
c9323cd564 ignore some invalid writes 2020-12-23 19:15:31 -05:00
Dillon Beliveau
572ff6a998 tlbr seems to work, so enable it 2020-12-23 19:14:36 -05:00
Dillon Beliveau
9b5a83201c more portable DMULT and DMULTU 2020-12-23 19:06:21 -05:00
Dillon Beliveau
d50742f8a2 free objects 2020-12-23 18:21:50 -05:00
Dillon Beliveau
91a0fdd697 mask address every time skip is added & correct length register value 2020-12-22 22:24:02 -05:00
Dillon Beliveau
b9dfa65e81 length reg in SP DMA writes as well 2020-12-22 21:58:31 -05:00
Dillon Beliveau
21d244ec02 improve mem force alignment in SP DMAs 2020-12-22 21:56:49 -05:00
Dillon Beliveau
51199cc0a0 SP DMA addresses are stored in shadow registers until the DMA runs 2020-12-22 21:46:10 -05:00
Dillon Beliveau
f28a336f5b these are one register on hardware 2020-12-22 21:02:39 -05:00
Dillon Beliveau
f5303cb5a8 combine cells 2020-12-22 20:29:44 -05:00
Dillon Beliveau
11bba27c24 change theme and formatting of some tables 2020-12-22 19:38:36 -05:00
Dillon Beliveau
d9cc6edc9d Every MIPS interface register documented 2020-12-22 00:53:16 -05:00
Dillon Beliveau
5f72ce7461 more MI docs 2020-12-22 00:42:41 -05:00
Dillon Beliveau
458ece5fe9 document one MI register 2020-12-22 00:14:02 -05:00
Dillon Beliveau
8e1bd59b04 back to interpreter for these tests 2020-12-21 20:33:50 -05:00
Dillon Beliveau
533e4a4294 JIT: dmult, dsra, bltzal 2020-12-21 19:46:59 -05:00
Dillon Beliveau
3ea6dde4a7 increment Count correctly in JIT 2020-12-21 19:31:46 -05:00
Dillon Beliveau
73560e4a0e BAILZERO macro 2020-12-20 17:20:51 -05:00
Dillon Beliveau
36cd6af3f8 remove logs 2020-12-20 17:17:48 -05:00
Dillon Beliveau
b54e223e1c sra 2020-12-20 17:11:09 -05:00
Dillon Beliveau
9d640f5a95 SEAX macro 2020-12-20 16:58:08 -05:00
Dillon Beliveau
6bcdc6b081 LOADRAX/SAVERAX macros 2020-12-20 16:54:19 -05:00
Dillon Beliveau
0146ae4361 sll/srl 2020-12-20 16:40:35 -05:00
Dillon Beliveau
e0c3f1ca3c ori/xori 2020-12-20 16:32:13 -05:00
Dillon Beliveau
e0f89a4775 reorganize 2020-12-20 16:23:31 -05:00
Dillon Beliveau
74f5a832ab faster compiler for andi 2020-12-20 16:16:56 -05:00
Dillon Beliveau
1122d6732c fix warning 2020-12-20 16:16:48 -05:00
Dillon Beliveau
5ab318ae72 macroin' and fixin' - (d)addi(u) shouldn't write to r0 2020-12-20 16:06:35 -05:00
Dillon Beliveau
b75d08ac59 fix addi/addiu 2020-12-20 15:52:23 -05:00
Dillon Beliveau
a675c11fd0 test_rom uses dynarec 2020-12-20 15:52:10 -05:00
Dillon Beliveau
f0c19ba275 addi/addiu don't use handlers at all 2020-12-20 14:43:09 -05:00
Dillon Beliveau
df4364c000 always bounds-check ROM 2020-12-17 23:43:41 -05:00
Dillon Beliveau
8eae9a3dda Function for releasing RSP semaphore 2020-12-17 23:42:58 -05:00
Dillon Beliveau
040bb6f0c6 Revert "don't queue samples if we already have a full second of audio available" 
This reverts commit eb6c41a592.
 2020-12-13 17:45:16 -05:00
Dillon Beliveau
0d9d680cbb latest version of parallel-rdp 2020-12-13 15:03:48 -05:00
Dillon Beliveau
8df492a53a load pif rom if it exists 2020-12-13 15:03:41 -05:00
Dillon Beliveau
fdd544e75b commented out definitions 2020-12-13 14:35:50 -05:00
Dillon Beliveau
55454cbad4 use MAIN_DEPENDENCY 2020-12-13 14:35:41 -05:00
Dillon Beliveau
3861a8e884 CMake updates to work with Ninja generator 2020-12-13 14:03:01 -05:00