Dillon Beliveau
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85bc8922b8
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continue using big endian for RSP
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2021-01-24 15:09:15 -05:00 |
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Dillon Beliveau
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942e67a34d
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rdram to little endian (cpu supported only), use mainline parallel-rdp
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2021-01-24 14:58:27 -05:00 |
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Dillon Beliveau
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c246c36511
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move stuff around, RSP bus doesn't need whole system
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2021-01-24 13:22:50 -05:00 |
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Dillon Beliveau
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c0d22f5f78
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delete some unused code
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2021-01-24 13:05:44 -05:00 |
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Dillon Beliveau
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a9a1fedf8b
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take RSP as argument here
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2021-01-24 12:50:14 -05:00 |
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Dillon Beliveau
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dfcd708978
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const
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2021-01-23 19:19:01 -05:00 |
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Dillon Beliveau
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5856ef7823
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close button on imgui demo window
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2021-01-23 13:44:28 -05:00 |
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Dillon Beliveau
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ccdb50728e
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update readme
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2021-01-23 13:32:02 -05:00 |
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Dillon Beliveau
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9b02ea87fc
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add -h / --help parameter
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2021-01-23 13:14:09 -05:00 |
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Dillon Beliveau
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fb9e659f42
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Add screenshot
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2021-01-23 12:59:10 -05:00 |
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Dillon Beliveau
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e3e8a4bc4c
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Remove screenshot
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2021-01-23 12:58:01 -05:00 |
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Dillon Beliveau
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5c7c3c3ffe
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cleanup useless comments
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2021-01-22 00:26:07 -05:00 |
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Dillon Beliveau
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087004f6bb
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Merge pull request #8 from Dillonb/imgui
Imgui
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2021-01-22 00:20:24 -05:00 |
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Dillon Beliveau
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f0e4dbc620
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don't destroy these
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2021-01-21 23:34:20 -05:00 |
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Dillon Beliveau
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ccdb94a97e
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use a renderpass, draw parallel-rdp's image to swapchain using a textured quad
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2021-01-21 23:21:18 -05:00 |
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Dillon Beliveau
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bdb492bcc5
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cleanup font upload code further
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2021-01-20 18:03:27 -05:00 |
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Dillon Beliveau
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be327a9539
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only run command buffer once
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2021-01-20 17:17:39 -05:00 |
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Dillon Beliveau
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23972be4a7
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Use ubuntu 20.04 for build pipeline
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2021-01-19 23:36:02 -05:00 |
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Dillon Beliveau
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d89fe8d29f
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add vulkan headers include path to imgui module
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2021-01-19 23:05:57 -05:00 |
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Dillon Beliveau
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3e481f3c2b
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UI tweaks
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2021-01-19 23:05:50 -05:00 |
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Dillon Beliveau
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395c842c58
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swapping between roms deals with different backup files correctly
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2021-01-19 22:12:08 -05:00 |
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Dillon Beliveau
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f687ac01b6
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file browser, and allow swapping out ROM
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2021-01-19 21:53:45 -05:00 |
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Dillon Beliveau
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58cb143f83
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Display UI on a blank screen when no ROM loaded
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2021-01-19 21:09:22 -05:00 |
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Dillon Beliveau
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6c51fca0b4
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imgui metrics with ImPlot
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2021-01-19 00:06:31 -05:00 |
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Dillon Beliveau
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b138a4de8b
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start working on UI
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2021-01-18 21:34:21 -05:00 |
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Dillon Beliveau
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9d002efc9f
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finally got imgui working
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2021-01-18 21:10:54 -05:00 |
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Dillon Beliveau
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1c9bb1a54c
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missed some zeroes
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2021-01-18 14:08:44 -05:00 |
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Dillon Beliveau
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dd8eb8d918
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use memcpy for HLEing the pif rom's DMA
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2021-01-17 17:08:24 -05:00 |
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Dillon Beliveau
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bf03a6219e
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buggy round instructions
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2021-01-17 16:47:24 -05:00 |
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Dillon Beliveau
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1901617402
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these were wrong, so mark them as unimplemented again
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2021-01-17 16:25:51 -05:00 |
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Dillon Beliveau
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fde580b70c
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stub cp1 round instructions
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2021-01-17 16:21:40 -05:00 |
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Dillon Beliveau
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78077e7e55
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exception updates & implement TRAP exception
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2021-01-17 15:35:35 -05:00 |
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Dillon Beliveau
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0d28224371
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do work in rax
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2021-01-17 15:06:25 -05:00 |
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Dillon Beliveau
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6bdaef1bc6
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these don't sign extend
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2021-01-17 14:21:13 -05:00 |
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Dillon Beliveau
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ed3b92c014
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dsrl32, dsra32
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2021-01-17 14:03:01 -05:00 |
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Dillon Beliveau
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e4747d501d
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fix doubleword shifts, add dsll32
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2021-01-17 14:01:46 -05:00 |
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Dillon Beliveau
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351b26f04f
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more fast versions of instructions
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2021-01-17 13:48:51 -05:00 |
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Dillon Beliveau
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5a0b1f551b
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Merge branch 'register-allocation'
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2021-01-17 12:44:01 -05:00 |
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Dillon Beliveau
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dfebb66bc1
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variable shifts, use al in slti(u)
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2021-01-17 12:34:25 -05:00 |
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Dillon Beliveau
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310d3669fb
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upgrade dynasm, don't use rcx for register allocation
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2021-01-17 12:25:04 -05:00 |
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Dillon Beliveau
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0da16e7289
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check and flush even when just loading one register
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2021-01-17 01:38:10 -05:00 |
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Dillon Beliveau
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84b2dd0b7d
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mfhi/mthi/mflo/mtlo, framework for r_type
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2021-01-17 01:34:58 -05:00 |
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Dillon Beliveau
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42a62a8c5f
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fast slti, sltiu, sll, srl, sra
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2021-01-17 00:57:36 -05:00 |
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Dillon Beliveau
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a86b429426
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more reorganizing and cleanup
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2021-01-16 23:43:27 -05:00 |
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Dillon Beliveau
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42a1a9214d
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just do the movsxd
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2021-01-16 23:40:41 -05:00 |
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Dillon Beliveau
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8ecc09f72a
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reorganize and cleanup
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2021-01-16 23:22:20 -05:00 |
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Dillon Beliveau
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06114a767b
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flush all regs after branch likely
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2021-01-16 23:16:57 -05:00 |
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Dillon Beliveau
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a87cb0cfbc
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andi + ori working
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2021-01-16 23:15:57 -05:00 |
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Dillon Beliveau
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0fa9a98bbc
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register allocation seems to be working, using only low registers for now
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2021-01-16 23:10:14 -05:00 |
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Dillon Beliveau
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2a4cebae80
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fast ori
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2021-01-16 20:59:25 -05:00 |
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