1192 commits

Author	SHA1	Message	Date
Dillon Beliveau	67ddbb2b6e	Disable terminal colors on Windows	2021-05-09 07:54:02 -04:00
Dillon Beliveau	6d364b3673	Windows CI	2021-05-08 17:40:35 -04:00
Dillon Beliveau	5930246cde	VirtualProtect to make codecache executable on Windows	2021-05-08 14:27:43 -04:00
Dillon Beliveau	1c2c75f36b	separate type of static assert for C++	2021-05-08 13:53:09 -04:00
Dillon Beliveau	a1028be3bb	Fix mips_instruction_t bitfield	2021-05-08 13:15:24 -04:00
Dillon Beliveau	9cb8637869	Remove duplicate assert	2021-05-08 12:57:49 -04:00
Dillon Beliveau	e2da4efa2b	Size assertion & use packed macro	2021-05-08 12:47:55 -04:00
Dillon Beliveau	d8c940f031	Another set of Windows fixes	2021-05-08 12:35:13 -04:00
Dillon Beliveau	cff8355f49	Merge branch 'master' into windows-port-take-2	2021-05-08 11:34:49 -04:00
Dillon Beliveau	e859c0c39c	fix build on linux	2021-05-08 11:28:41 -04:00
Dillon Beliveau	d37912122d	treat SYNC instruction as NOP	2021-05-07 15:08:23 -04:00
Dillon Beliveau	11604a81e6	fix analog stick clamping for real this time	2021-05-07 14:43:13 -04:00
Dillon Beliveau	4d6428bbe2	improve gamepad experience a bit	2021-05-07 13:43:11 -04:00
Dillon Beliveau	008362c212	6103/7103 writes RDRAM size to 0x318	2021-05-05 15:45:34 -04:00
Dillon Beliveau	f9b1ae590b	log CIC information when rom loaded	2021-05-05 15:45:14 -04:00
Dillon Beliveau	3d02129038	quiet down audiostream buffer underflow warnings	2021-05-05 15:27:53 -04:00
Dillon Beliveau	cb2f142140	support 0xFE and 0xFD bytes in PIF RAM	2021-05-05 15:13:32 -04:00
Dillon Beliveau	79d08af60a	typo	2021-04-28 13:32:58 -04:00
Dillon Beliveau	0352f0142e	calculate framebuffer height with vi_vstart instead of vi_yscale	2021-04-28 13:21:11 -04:00
Dillon Beliveau	a5f30c68c6	handle interlaced video correctly	2021-04-25 17:19:57 -04:00
Dillon Beliveau	a8dedc0b1b	skip 0xFE commands	2021-04-25 12:48:10 -04:00
Dillon Beliveau	06f724fd5e	break instruction in interpreter	2021-04-24 19:15:20 -04:00
Dillon Beliveau	9324c64ae3	fix mempack read/write handling with out of range addresses	2021-04-24 17:45:56 -04:00
Dillon Beliveau	f63999a62c	allow setting ERROR_EPC	2021-04-24 17:45:41 -04:00
Dillon Beliveau	d806b30b33	BREAK instruction in CPU	2021-04-24 17:45:33 -04:00
Dillon Beliveau	dbc163f883	don't ever set rdp freeze to 1	2021-04-24 13:51:01 -04:00
Dillon Beliveau	e874b32794	pif improvements, cic 6105 challenge/response implementation	2021-04-24 13:40:14 -04:00
Dillon Beliveau	a8db586749	joystick doesn't actually use the full 8 bit range	2021-04-24 11:15:37 -04:00
Dillon Beliveau	3ed1b98f5a	force align RDP command lists	2021-04-23 18:50:19 -04:00
Dillon Beliveau	e3bb0726ec	ignore invalid flash commands	2021-04-18 16:08:15 -04:00
Dillon Beliveau	ec26947761	toggle framerate unlocking with u	2021-04-18 15:26:40 -04:00
Dillon Beliveau	5c14b361d4	div fix INT_MIN/-1, ddiv fix divide by zero	2021-04-18 14:34:11 -04:00
Dillon Beliveau	f0ace0c79a	fix div/divu	2021-04-18 14:06:58 -04:00
Dillon Beliveau	69102d37f0	divu/ddivu fixes	2021-04-18 13:47:15 -04:00
Dillon Beliveau	e54955317a	only persist mempack data if any data changed	2021-04-17 09:46:40 -04:00
Dillon Beliveau	d6a54a9323	j/jal actually work in 64 bit mode	2021-04-17 09:21:55 -04:00
Dillon Beliveau	8a007f104e	j/jal work in 64 bit mode	2021-04-17 09:08:54 -04:00
Dillon Beliveau	02431a272d	WWF: No Mercy to game db	2021-04-17 09:04:15 -04:00
Dillon Beliveau	8e9c4a88e1	DSRAV uses the low 6 bits	2021-04-11 21:04:53 -04:00
Dillon Beliveau	a907738f36	rdram dump code to n64mem.c	2021-04-11 16:09:23 -04:00
Dillon Beliveau	54a65197dd	set entry hi correctly	2021-04-10 16:59:41 -04:00
Dillon Beliveau	8d93188339	bump upper bound	2021-04-10 16:24:02 -04:00
Dillon Beliveau	d0618585f0	tlbwr + tlb exceptions on lwc1	2021-04-10 15:45:54 -04:00
Dillon Beliveau	cb47db1c34	TLB exceptions kinda working	2021-04-10 15:05:28 -04:00
Dillon Beliveau	382f9ededc	Ogre battle 64 to game db	2021-04-10 12:01:16 -04:00
Dillon Beliveau	21664896ec	dump TLB state on errors	2021-04-10 12:01:00 -04:00
Dillon Beliveau	389904a311	0x05xxxxxx is the 64DD	2021-04-10 10:03:11 -04:00
Dillon Beliveau	734586bdea	need to go through DMA to access SRAM	2021-04-10 01:41:28 -04:00
Dillon Beliveau	a46a734d14	DSRAV	2021-04-10 01:17:52 -04:00
Dillon Beliveau	c0e1607df9	initialize SRAM to all 0xFFs	2021-04-10 00:51:37 -04:00