Emulation/n64
1
0
Fork 0
mirror of https://github.com/Dillonb/n64.git synced 2025-04-02 10:42:08 -04:00
Code Issues Projects Releases Packages Wiki Activity
1381 commits 16 branches 0 tags 17 MiB
Commit graph

1192 commits

Author SHA1 Message Date
Dillon Beliveau
c62016aaf9 Simplify TLB registers' masking code 2022-06-11 17:42:07 -07:00
Dillon Beliveau
b6d51f07af quiet! 2022-06-11 17:17:05 -07:00
Dillon Beliveau
8576eaafde Simplify page mask masking logic 2022-06-11 16:41:50 -07:00
Dillon Beliveau
f7969a8444 replace load/store bools with bus_access_t enum 2022-06-11 16:37:00 -07:00
Dillon Beliveau
9295edb8e1 TLB miss exceptions in LH 2022-06-11 16:28:50 -07:00
Dillon Beliveau
8d40b774ab Unused CP0 registers are a single register 2022-06-11 15:46:11 -07:00
Dillon Beliveau
47840896fe CKSEG3 2022-06-11 15:26:33 -07:00
Dillon Beliveau
b9e4a0e1e2 reserved instruction exception 2022-06-11 15:26:22 -07:00
Dillon Beliveau
1d15877f3b Support for TLB exceptions in more instructions, implement XKSEG 2022-06-11 15:12:44 -07:00
Dillon Beliveau
2bd0c760fb TLB exceptions in LL 2022-06-11 14:51:37 -07:00
Dillon Beliveau
ea2d27b447 more TLB fixes 2022-06-11 14:50:12 -07:00
Dillon Beliveau
f7400a7438 TLB fixes 2022-06-11 14:02:04 -07:00
Dillon Beliveau
92b94ecc08 TLBR reads page mask 2022-06-11 12:33:14 -07:00
Dillon Beliveau
bca5d22733 typo 2022-06-11 11:53:52 -07:00
Dillon Beliveau
5fd3da320f fix some cop0 masking and the random/wired registers 2022-06-11 10:42:50 -07:00
Dillon Beliveau
bed9a97b7c Set prev branch flag when needed in dynarec 2022-06-10 20:46:52 -07:00
Dillon Beliveau
7ca66ccf9f Set and use branch_likely_taken flag in dynarec instead of piggybacking on branch flag 2022-06-10 20:33:07 -07:00
Dillon Beliveau
92dbfbd5a9 fix exceptions inside branch delay slots 2022-06-10 19:37:06 -07:00
Dillon Beliveau
4978d2a15a fix ai address increment 2022-06-09 22:40:37 -07:00
Dillon Beliveau
c844f9bc73 fix signed overflow check to be more reliable 2022-06-06 01:11:28 -07:00
Dillon Beliveau
59649b1601 bad_vaddr is read only 2022-06-06 00:37:40 -07:00
Dillon Beliveau
63ad3ea449 address error fixes, context/xcontext masking on writes 2022-06-05 23:59:57 -07:00
Dillon Beliveau
2da81b073e address errors in SW 2022-06-05 22:49:33 -07:00
Dillon Beliveau
f109365215 fix address error exceptions 2022-06-05 22:39:14 -07:00
Dillon Beliveau
7843efe895 fix cast 2022-06-05 16:22:06 -07:00
Dillon Beliveau
718a8ec3cf don't logalways 2022-06-05 15:31:39 -07:00
Dillon Beliveau
3ed1ec641e fix 64 bit CAUSE writes, set coprocessor_error to zero in CAUSE when the error is not with any coprocessor 2022-06-05 15:19:53 -07:00
Dillon Beliveau
da54e19af6 more TRAP instructions 2022-06-05 15:16:26 -07:00
Dillon Beliveau
fc02b2a078 TLB exceptions in SW 2022-06-05 14:28:56 -07:00
Dillon Beliveau
40afb9c887 remove asserts, implement/stub a few things to get n64-systemtest sans TLB/trap tests to run with the interpreter 2022-06-05 14:20:13 -07:00
Dillon Beliveau
447c0c89a1 mask cl in srav in jit 2022-01-16 14:08:24 -08:00
Dillon Beliveau
f3cd487021 generate rs,rt,rd tests 2022-01-16 14:08:11 -08:00
Dillon Beliveau
0af9953335 fix sra/srav in jit as well 2022-01-15 17:07:49 -08:00
Dillon Beliveau
1dce496991 Support generating shift test cases, fix sra and srav 2022-01-15 17:05:22 -08:00
Dillon Beliveau
e93e3ddabe shift rsp pc correctly when reading from the CPU 2022-01-08 11:50:34 -08:00
Dillon Beliveau
25cbbc71b1 move ERET to mips_instructions.c 2021-12-28 17:22:43 -08:00
Dillon Beliveau
fc851e5f54 Maintain aspect ratio when resizing window 2021-12-19 18:02:26 -08:00
Dillon Beliveau
2d66075ec1 Compile blit shaders instead of hardcoding 2021-12-19 17:06:52 -08:00
Dillon Beliveau
83b77683ce Reset RSP PC to 0 when resetting 2021-11-06 10:22:41 -07:00
simuuz
053391ea2f hang at n64rom.c:162 2021-10-06 21:16:46 +02:00
simuuz
baaee9ecc6 starting work on GUI 2021-10-06 21:04:23 +02:00
Dillon Beliveau
88efacf56f Fix compiler warnings 2021-09-20 21:08:06 -04:00
Dillon Beliveau
3284e9c570 Explicitly codify unknown SI registers 2021-09-20 21:08:00 -04:00
Dillon Beliveau
eca6841209 mask pif address, allow reading more si regs 2021-09-20 20:58:29 -04:00
Dillon Beliveau
746a40c0e0 Use SDL mutexes instead of my own platform specific code 2021-09-18 16:58:07 -04:00
Dillon Beliveau
dbe4e13580 jalr links to rd, not lr 2021-09-18 16:53:39 -04:00
Dillon Beliveau
f97065e73b Don't need an instance of SDL_Joystick 2021-09-18 16:53:20 -04:00
Dillon Beliveau
7184a649be Register access optimizations 2021-08-26 19:43:22 -04:00
ITotalJustice
c2e4c94a2d
typedef SDL_PixelFormatEnum if SDL version is < 2.0.10 2021-06-10 22:11:44 +01:00
Dillon Beliveau
748f5017b9 PI DMA alignment improvements 2021-06-08 17:54:12 -04:00