205 commits

Author	SHA1	Message	Date
Dillon Beliveau	0845fb6ef1	lld in interpreter	2020-12-28 18:37:49 -05:00
Dillon Beliveau	05a0c81088	register size fixes	2020-12-28 18:11:16 -05:00
Dillon Beliveau	31936ecc2a	don't lower interrupts randomly	2020-12-27 02:14:57 -05:00
Dillon Beliveau	999562468c	mask Count reg	2020-12-27 02:14:49 -05:00
Dillon Beliveau	9ef2d59872	RI regs are writable, and are initialized to certain values	2020-12-27 02:08:33 -05:00
Dillon Beliveau	6e8bfa93fd	frameworking out 64 bit addressing	2020-12-26 22:19:21 -05:00
Dillon Beliveau	5f7399bc7d	log rom name	2020-12-26 18:35:42 -05:00
Dillon Beliveau	34fc64a2d5	CP0 fixes	2020-12-26 18:33:48 -05:00
Dillon Beliveau	e228958190	slower, but hopefully more accurate, RSP timing	2020-12-26 15:20:06 -05:00
Dillon Beliveau	7674bd1cac	exception fixes/updates	2020-12-25 20:22:25 -05:00
Dillon Beliveau	861e04d5e6	allow switching between jit and interpreter without recompiling, debug mode forces interpreter	2020-12-25 14:43:21 -05:00
Dillon Beliveau	348aad1777	RSP timing tweaks	2020-12-24 18:06:44 -05:00
Dillon Beliveau	5583d4fe22	turn on debug logging when USR1 signal received	2020-12-24 00:06:41 -05:00
Dillon Beliveau	608ec61486	only inc count in one place	2020-12-23 19:50:06 -05:00
Dillon Beliveau	d50742f8a2	free objects	2020-12-23 18:21:50 -05:00
Dillon Beliveau	3ea6dde4a7	increment Count correctly in JIT	2020-12-21 19:31:46 -05:00
Dillon Beliveau	a675c11fd0	test_rom uses dynarec	2020-12-20 15:52:10 -05:00
Dillon Beliveau	cc87506698	reset cpu steps to zero to not run too many RSP steps when it's enabled after being disabled for a while	2020-12-13 01:40:08 -05:00
Dillon Beliveau	3f05940cbf	logtester updates to read jit sync logs	2020-12-12 23:52:36 -05:00
Dillon Beliveau	71c50af370	use same new timing code in the interpreter as the jit	2020-12-08 01:58:30 -05:00
Dillon Beliveau	be12de010f	correct initial value of CP0 status	2020-12-08 00:06:58 -05:00
Dillon Beliveau	25e269c722	new structure for holding FPRs	2020-12-07 22:55:11 -05:00
Dillon Beliveau	6b68f130c0	RDRAM aligned to a page boundary	2020-12-06 01:40:13 -05:00
Dillon Beliveau	ce741f13fb	Don't check every single RSP cycle if an instruction needs to be decoded	2020-12-05 20:48:04 -05:00
Dillon Beliveau	58dd32d194	cleanup includes	2020-12-05 20:02:28 -05:00
Dillon Beliveau	bde41c7684	rework RSP timing	2020-12-05 20:00:09 -05:00
Dillon Beliveau	b1988d9d34	fix more sanitizer-detected issues	2020-12-01 22:03:33 -05:00
Dillon Beliveau	acc25b3547	determine CIC type and write to PIF RAM. the PIF ROM now boots.	2020-11-25 11:51:03 -05:00
Dillon Beliveau	13350bf1d2	fix dpc status bitfield	2020-11-21 21:43:32 -05:00
Dillon Beliveau	f98f84ce21	parallel-rdp process display lists	2020-11-21 01:13:36 -05:00
Dillon Beliveau	a6ea87bf34	finish initialization of vulkan stuff, start wiring things up	2020-11-14 14:04:36 -05:00
Dillon Beliveau	f97396ca2b	Merge branch 'master' into parallel-rdp	2020-11-10 19:55:18 -05:00
Dillon Beliveau	6917c0560c	Automatically run test roms if repo cloned	2020-10-24 19:22:29 -04:00
Dillon Beliveau	8f8827f91e	stub stuff for parallel-rdp and vulkan	2020-10-04 12:17:05 -04:00
Dillon Beliveau	f41bbef60b	don't even call RSP if it's halted	2020-10-03 19:49:08 -04:00
Dillon Beliveau	50021b5a23	hopefully slightly faster RSP / CPU timing sync	2020-10-03 19:46:39 -04:00
Dillon Beliveau	e655109e80	some logwarns to loginfo	2020-10-03 14:26:14 -04:00
Dillon Beliveau	e93f2c4d46	RSP cannot read/write DWORDs	2020-10-03 14:20:43 -04:00
Dillon Beliveau	edbf24dd7a	perform all RSP steps at once without repeatedly calling	2020-10-02 10:56:36 -04:00
Dillon Beliveau	f50a4e5595	exit block early on CP1 unusable exceptions	2020-10-01 22:08:09 -04:00
Dillon Beliveau	aebf4ca4f4	cleanup, 128MiB code cache	2020-09-28 23:29:20 -04:00
Dillon Beliveau	e164db7caa	fix dynarec	2020-09-28 22:50:50 -04:00
Dillon Beliveau	b008630ccf	cached interpreter works, exceptions still broken	2020-09-26 19:35:53 -04:00
Dillon Beliveau	9702287e7b	cached interpreter can generate a block and call it	2020-09-26 16:50:47 -04:00
Dillon Beliveau	5b2d33cf9c	beginnings of a dynarec/cached interpreter	2020-09-25 22:39:26 -04:00
Dillon Beliveau	5670c28aa1	don't use instruction type enum in RSP, use function pointers	2020-09-24 19:27:48 -04:00
Dillon Beliveau	e1d2b824ed	optimizing	2020-09-23 22:51:40 -04:00
Dillon Beliveau	6bb62ddbfa	changes to CPU/RSP syncing	2020-09-23 22:28:39 -04:00
Dillon Beliveau	b9d718fd61	remove some indirection around reading words	2020-09-23 22:27:18 -04:00
Dillon Beliveau	4325daec02	vsync back on, better cycles_per_instr support	2020-09-23 00:44:39 -04:00