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1859 commits 16 branches 0 tags 17 MiB
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205 commits

Author SHA1 Message Date
Kevin K
4ed6ae72d2
fix: pack -> pak 2024-02-25 03:49:32 +01:00
Dillon Beliveau
91c198fe60 support fully disabling dynarec 2023-08-27 23:46:50 -07:00
Dillon Beliveau
9f1e3f0df7 Allow building without dynarec v1 2023-08-27 23:21:01 -07:00
Dillon Beliveau
b831c8e8e9 include failure message in the crash dump 2023-08-27 21:00:13 -07:00
Dillon Beliveau
ca9585b526 Support for saving crash dumps 2023-08-27 20:40:51 -07:00
Dillon Beliveau
5c6a7b6a25 basic idle loop detection 2023-08-25 20:23:38 -07:00
Dillon Beliveau
dae333377b Merge branch 'master' into dynarec_v2 2023-07-22 18:22:55 -07:00
Dillon Beliveau
fe8b0a59b6 support for logging CPU state 2023-07-22 17:04:47 -07:00
Dillon Beliveau
985c615249 fix count reg in matchjit interpreter 2023-07-22 15:06:19 -07:00
Dillon Beliveau
744d8ed655 use macros for format strings 2023-07-16 18:45:48 -07:00
Dillon Beliveau
22ce68e83d interrupt timing issues 2023-07-15 12:49:45 -07:00
Dillon Beliveau
e55c144fad various jit fixes 2023-05-27 15:56:12 -07:00
Dillon Beliveau
02caf5560d interrupts on the scheduler 2023-05-13 14:29:14 -07:00
Dillon Beliveau
a31d7489cc Merge branch 'master' into dynarec_v2 2023-04-29 14:12:01 -07:00
Dillon Beliveau
8b9dccfdaa VI timing on scheduler 2023-04-29 14:04:54 -07:00
Dillon Beliveau
b9801847ed dynarec compare fixes + support for tas movies 2023-04-16 14:44:46 -07:00
Dillon Beliveau
b17ef7eb29 fix tests 2023-03-19 01:43:11 -07:00
Dillon Beliveau
b920127cfd clear FCR31 flag and cause in interpreter, when comparing 2023-03-18 17:30:33 -07:00
Dillon Beliveau
ce699fe528 Explicit error when scheduler event nodes are exhausted 2023-03-18 14:24:22 -07:00
Dillon Beliveau
b2803666d1 match JIT RSP behavior in interpreter, if we are comparing the jit vs. the interpreter 2023-03-18 13:51:28 -07:00
Dillon Beliveau
e62fb04403 check that interpreter and jit are in sync, zero cost exceptions 2023-03-11 12:31:02 -08:00
Dillon Beliveau
1c37494031 init settings in dynarec compare, only check vi interrupts when v_current changes, allow quitting in dynarec compare 2023-03-11 11:10:45 -08:00
Dillon Beliveau
6d7ab0e4d6 fix 2023-03-11 00:49:55 -08:00
Dillon Beliveau
f1d1f5106a WIP 2023-03-10 18:49:59 -08:00
Dillon Beliveau
35694c7842 statically allocate dynarec 2023-03-07 00:57:28 -08:00
Dillon Beliveau
9475b6570b emit dispatcher at runtime 2023-03-06 00:01:39 -08:00
Dillon Beliveau
0b6c26be4f cleanup 2023-03-04 17:49:10 -08:00
Dillon Beliveau
8678084991 remove logfatal 2023-02-22 00:17:58 -08:00
Dillon Beliveau
c9b5ac6296 refactor interpreter to allow running the CPU for more than a single cycle at a time 2023-02-20 15:33:04 -08:00
Dillon Beliveau
5c3cd84b5e timing slightly more accurate in n64_system_step 2023-02-20 13:14:39 -08:00
Dillon Beliveau
4c268f80d2 dynarec_compare improvements: copy sp dmem and imem, vi timing and interrupts 2023-02-18 20:39:44 -08:00
Dillon Beliveau
9925f84572 dynarec_compare tool 2023-02-11 21:02:21 -08:00
Dillon Beliveau
7e44ce82b7 Stall CPU when reading from PI bus latch 2022-09-10 15:34:21 -07:00
Dillon Beliveau
37803b4de5 Settings support 2022-08-20 15:45:44 -07:00
Dillon Beliveau
66d943e6cb DPC interface fixes 2022-08-13 16:48:08 -07:00
Dillon Beliveau
b35dc036c0 Remove mupen64plus RDP plugin support 2022-08-13 16:33:37 -07:00
Dillon Beliveau
a80c664c29 Implement PI bus latching 2022-08-08 22:55:31 -07:00
Dillon Beliveau
b57e9f47b6 Remove redundant members 2022-07-31 15:34:51 -07:00
Dillon Beliveau
da63604467 PAL games run at 50fps 2022-07-24 16:56:54 -07:00
Dillon Beliveau
af16ad1712 Replace dword with u64 2022-07-23 17:18:30 -07:00
Dillon Beliveau
71d9365bed Update integer type names 2022-07-13 19:24:09 -07:00
Dillon Beliveau
07e68cd2cf Reset menu item working 2022-07-11 21:05:09 -07:00
Dillon Beliveau
e502256f3f parallel-rdp rendering inside Qt 2022-07-10 16:03:35 -07:00
Dillon Beliveau
6d5906487c WIP, need to figure out the swapchain 2022-07-02 20:31:14 -07:00
Dillon Beliveau
c4ea8a3ed5 many small fixes, including separate memory map for user mode 2022-06-12 19:17:25 -07:00
Dillon Beliveau
b0a5d646ba use coprocessor error 0 instead of -1 everywhere 2022-06-12 14:05:16 -07:00
Dillon Beliveau
5fd3da320f fix some cop0 masking and the random/wired registers 2022-06-11 10:42:50 -07:00
Dillon Beliveau
bed9a97b7c Set prev branch flag when needed in dynarec 2022-06-10 20:46:52 -07:00
Dillon Beliveau
92dbfbd5a9 fix exceptions inside branch delay slots 2022-06-10 19:37:06 -07:00
Dillon Beliveau
4978d2a15a fix ai address increment 2022-06-09 22:40:37 -07:00