1859 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Dillon Beliveau	cc934dfb9b	Merge branch 'master' into rsp_dynarec_v2	2024-02-24 18:55:24 -08:00
Dillon Beliveau	bfcf63989e	fix formatting	2024-02-24 18:53:55 -08:00
Dillon Beliveau	7e948b8217	Merge pull request #49 from xkevio/patch-1 ... fix: `pack` -> `pak`	2024-02-24 18:52:12 -08:00
Kevin K	4ed6ae72d2	fix: pack -> pak	2024-02-25 03:49:32 +01:00
Dillon Beliveau	6f651209d4	add include	2023-12-28 17:05:57 +01:00
Dillon Beliveau	9181f5445c	Remove SCHEDULER_HANDLE_INTERRUPT event before queueing a new one	2023-10-18 00:55:17 -07:00
Dillon Beliveau	f570771e57	stub vmulf and ir instruction to get VTE	2023-09-24 12:51:05 -07:00
Dillon Beliveau	8d0f140e0f	fix IR_VPR_INSERT	2023-09-17 23:00:10 -07:00
Dillon Beliveau	1ecbe0b3ad	stub CP2, new IR instruction for inserting into the middle of a VPR, WIP MTC2	2023-09-17 20:09:06 -07:00
Dillon Beliveau	43b38f7950	oops	2023-09-16 18:56:24 -07:00
Dillon Beliveau	82e19a9bf4	WIP SDV	2023-09-16 13:03:26 -07:00
Dillon Beliveau	0c8214ed63	oops	2023-09-12 20:39:03 -07:00
Dillon Beliveau	881f63fca6	remove an instruction	2023-09-12 20:07:17 -07:00
Dillon Beliveau	4c83d62e68	fix LDV	2023-09-11 22:42:56 -07:00
Dillon Beliveau	d3a2b5ee79	add missing calls to reset_temp_vpr	2023-09-11 22:21:00 -07:00
Dillon Beliveau	c5c962be33	refactor common code, implement lbv and lsv	2023-09-11 22:19:13 -07:00
Dillon Beliveau	e6c0d04a80	finish stubbing remaining bector loads	2023-09-11 21:23:24 -07:00
Dillon Beliveau	3a5a85dd81	set code mask correctly	2023-09-11 21:17:03 -07:00
Dillon Beliveau	bbe5cf3b42	stub remaining vector loads	2023-09-11 01:23:03 -07:00
Dillon Beliveau	533d188afb	stub remaining vector stores	2023-09-11 01:15:12 -07:00
Dillon Beliveau	0ff381b936	use macros	2023-09-11 00:53:46 -07:00
Dillon Beliveau	83fda35a84	fix macro	2023-09-11 00:46:42 -07:00
Dillon Beliveau	b954a31af4	sqv	2023-09-10 23:04:30 -07:00
Dillon Beliveau	d27bd3ff9a	add a monster comment	2023-09-10 21:48:55 -07:00
Dillon Beliveau	2fdd688a41	shrink regs used	2023-09-10 21:26:45 -07:00
Dillon Beliveau	65b0dbfe5d	finish LQV	2023-09-10 21:24:16 -07:00
Dillon Beliveau	0d9f1fb154	remove commented code	2023-09-10 16:42:24 -07:00
Dillon Beliveau	984f739f77	improve LQV, fix disassembly of LWC2/SWC2	2023-09-10 15:42:56 -07:00
Dillon Beliveau	de83d0e5bd	wip SDV, work LDV and LQV	2023-09-09 17:38:12 -07:00
Dillon Beliveau	f5297ca9ad	lqv	2023-09-08 20:40:41 -07:00
Dillon Beliveau	6960103bad	flush VPRs, implement LDV probably incorrectly	2023-09-08 19:48:43 -07:00
Dillon Beliveau	1de96772fe	WIP LDV, stub LQV	2023-09-07 23:49:22 -07:00
Dillon Beliveau	0f713d0968	bypass capstone for unique RSP instructions	2023-09-07 23:44:04 -07:00
Dillon Beliveau	b2f9f05cbd	stub SDV	2023-09-07 21:32:24 -07:00
Dillon Beliveau	ed66071bac	stub LDV	2023-09-07 20:44:16 -07:00
Dillon Beliveau	ff0710cc08	stub vector register type	2023-09-07 19:55:38 -07:00
Dillon Beliveau	0fcf59b5a1	some more stubbing	2023-09-05 00:15:27 -07:00
Dillon Beliveau	2155afa2f2	Merge branch 'master' into rsp_dynarec_v2	2023-09-04 21:59:58 -07:00
Dillon Beliveau	42e5ad9887	Fix RSP tests	2023-09-04 21:59:45 -07:00
Dillon Beliveau	ba8aaa8e78	better RSP loads	2023-09-04 20:21:56 -07:00
Dillon Beliveau	7ddcb58756	implement RSP break	2023-09-04 18:06:27 -07:00
Dillon Beliveau	c8caf7a25c	Merge branch 'master' into rsp_dynarec_v2	2023-09-04 16:55:58 -07:00
Dillon Beliveau	cf9a1bde4a	switch DMEM back to big endian	2023-09-04 16:55:45 -07:00
Dillon Beliveau	0c5d994456	more RSP instructions, stub out vector load/stores	2023-09-04 15:56:09 -07:00
Dillon Beliveau	1bbdf188f0	correct memory loads for RSP	2023-09-04 13:04:10 -07:00
Dillon Beliveau	60a6d95b46	implement more RSP instructions in JIT, stub out a bunch more	2023-09-04 12:49:16 -07:00
Dillon Beliveau	7b1958a92f	fix COP0 register names for the RSP	2023-09-04 01:57:22 -07:00
Dillon Beliveau	fc979a6fb9	RSP JIT: beq, lw, andi	2023-09-04 01:41:36 -07:00
Dillon Beliveau	6020e5af3f	RSP run_block function, make JIT more generic and support RSP better, ADDI in RSP JIT	2023-09-04 01:00:58 -07:00
Dillon Beliveau	43ddd315d0	rsp J opcode, compile RSP register loads correctly	2023-09-03 12:02:05 -07:00