1066 commits

Author	SHA1	Message	Date
Dillon Beliveau	40bcfe6257	oops	2023-02-20 16:54:26 -08:00
Dillon Beliveau	e69edd528c	macro for blockcache outer index	2023-02-20 16:37:24 -08:00
Dillon Beliveau	81de6a8638	fix coprocessor instruction decoding	2023-02-20 16:21:25 -08:00
Dillon Beliveau	c9b5ac6296	refactor interpreter to allow running the CPU for more than a single cycle at a time	2023-02-20 15:33:04 -08:00
Dillon Beliveau	5034d33fd3	ldl, ldr	2023-02-20 03:20:43 -08:00
Dillon Beliveau	759f633c0f	don't expand notted consts	2023-02-20 02:47:08 -08:00
Dillon Beliveau	317b701f28	swl, swr, empty emitters for ldl, ldr, sdl, sdr	2023-02-20 02:46:06 -08:00
Dillon Beliveau	54f2e7658c	lwl/lwr	2023-02-20 02:41:00 -08:00
Dillon Beliveau	6c0ac17d8d	bltzl, bgtzl	2023-02-20 00:25:14 -08:00
Dillon Beliveau	006c99c8a4	mfc0 compare, count	2023-02-20 00:11:23 -08:00
Dillon Beliveau	8d6da6281f	bgezl	2023-02-20 00:11:12 -08:00
Dillon Beliveau	f934dc0b6c	s32 multiplies	2023-02-20 00:11:04 -08:00
Dillon Beliveau	44b71566a6	cmp reg, imm works with spilled values	2023-02-20 00:10:55 -08:00
Dillon Beliveau	b13c557498	split FPU emitters into a separate source file	2023-02-20 00:10:41 -08:00
Dillon Beliveau	f3e794a6e5	fix and reg, imm with spilled reg	2023-02-19 16:41:18 -08:00
Dillon Beliveau	26a9404ec1	support reading EPC	2023-02-19 14:55:17 -08:00
Dillon Beliveau	19bdc159fa	add reg, reg works with spilled registers	2023-02-19 14:55:03 -08:00
Dillon Beliveau	29eb052d7a	IR_SET_PTR compiles correctly	2023-02-19 14:44:28 -08:00
Dillon Beliveau	d7d013a8a0	fix IR_SET_PTR always being optimized out	2023-02-19 14:44:03 -08:00
Dillon Beliveau	c2cabea407	eret	2023-02-19 14:27:07 -08:00
Dillon Beliveau	c9cca55226	replace get_mult_result with get_ptr, add mthi, mfc0 fixes and additions, more const shifts, stack alignment	2023-02-19 04:14:00 -08:00
Dillon Beliveau	a11cda4f1f	mfc0 cause, cmp reg reg for spilled regs, flush spilled regs	2023-02-19 03:36:39 -08:00
Dillon Beliveau	6c1108622d	sub const, reg	2023-02-19 03:28:08 -08:00
Dillon Beliveau	f2f115ce1f	constant propagation for logical right shift 32 bit	2023-02-18 21:25:36 -08:00
Dillon Beliveau	4cf8825581	remove CP0-specific IR instructions, add bgez, more mfc0 and mtc0 stuff	2023-02-18 21:23:09 -08:00
Dillon Beliveau	1e46858246	MTC0 stuff, ignore TLBWI	2023-02-18 21:00:11 -08:00
Dillon Beliveau	b1a66e7da4	alloc spilled register correctly	2023-02-18 20:59:42 -08:00
Dillon Beliveau	6a3a206269	oops	2023-02-18 20:41:25 -08:00
Dillon Beliveau	c0c1f1af6d	bltz should not link	2023-02-18 20:39:55 -08:00
Dillon Beliveau	1618062a91	div, more spilled reg handling	2023-02-18 19:44:39 -08:00
Dillon Beliveau	29492f76f9	register allocation fixes, mult with two variable regs, handle spilled regs in more cases	2023-02-18 17:54:30 -08:00
Dillon Beliveau	d9832061ff	pass full register allocation information to emitters, spill to stack	2023-02-18 16:30:36 -08:00
Dillon Beliveau	5633bf4431	Rewrite register allocation algorithm	2023-02-18 14:03:35 -08:00
Dillon Beliveau	3c22197660	bltz, mult, sub	2023-02-15 23:56:11 -08:00
Dillon Beliveau	ffe720bb65	sb, blez	2023-02-14 21:59:08 -08:00
Dillon Beliveau	213fde13ca	fix less than and greater than conditions	2023-02-14 21:54:35 -08:00
Dillon Beliveau	cac306a042	breakpoints in v2 compiler	2023-02-14 21:54:07 -08:00
Dillon Beliveau	d25da46e4a	block browser improvements	2023-02-14 21:53:36 -08:00
Dillon Beliveau	ee4d709b53	cfc1, ctc1, ignore FPU instructions	2023-02-12 21:42:48 -08:00
Dillon Beliveau	2fd89ed5e5	compile set cp0 status	2023-02-12 19:37:23 -08:00
Dillon Beliveau	70b9a50e50	Distinguish valid immediates from constants in the compiler. Compile MFC0	2023-02-12 18:18:53 -08:00
Dillon Beliveau	b297034494	check registers in host emitters	2023-02-12 18:10:18 -08:00
Dillon Beliveau	1e553cebbb	DSLL, DSLL32, DSRA, DSRA32, SRA, SRAV, DSLLV, NOR, XORI, SLTI, SLTIU	2023-02-12 16:15:00 -08:00
Dillon Beliveau	4d7d9666ab	fix ir_emit_link	2023-02-12 16:13:09 -08:00
Dillon Beliveau	b9bb72eb56	DADDIU	2023-02-12 15:08:36 -08:00
Dillon Beliveau	deb17652a8	LWU and DADDI	2023-02-12 15:06:37 -08:00
Dillon Beliveau	f0025cb5b7	handle const conditions in cond block exit, fix branch likely cond negation, implement BEQL	2023-02-12 15:04:38 -08:00
Dillon Beliveau	95bf422688	don't allow binding r0 to a value	2023-02-12 14:16:06 -08:00
Dillon Beliveau	804ed3d702	fix types for VALUE_TYPE_U16	2023-02-12 14:15:56 -08:00
Dillon Beliveau	fac8224a3f	move v2_link_and_encode into a separate TU	2023-02-12 14:15:39 -08:00