1066 commits

Author	SHA1	Message	Date
Dillon Beliveau	390175bafd	dynarec prologue/epilogue fixes, dangling pointer fix	2023-03-07 09:52:05 -08:00
Dillon Beliveau	35694c7842	statically allocate dynarec	2023-03-07 00:57:28 -08:00
Dillon Beliveau	c75cecb156	macro for function prologue and epilogue	2023-03-06 23:10:28 -08:00
Dillon Beliveau	870cc35c8f	don't disassemble run_block	2023-03-06 23:10:13 -08:00
Dillon Beliveau	c7a6503bd9	set run block fp inside init function	2023-03-06 23:01:26 -08:00
Dillon Beliveau	336f4c21b7	Many dynarec fixes, partially to work around a strange stack corruption issue seeming to come from dynasm	2023-03-06 22:59:17 -08:00
Dillon Beliveau	9475b6570b	emit dispatcher at runtime	2023-03-06 00:01:39 -08:00
Dillon Beliveau	4521eeaa36	common min/max functions	2023-03-05 12:54:12 -08:00
Dillon Beliveau	013f04c9e4	more fpu compares	2023-03-05 12:54:12 -08:00
Dillon Beliveau	1ac424d986	64 bit multiplies and divides, spilling fixes, cp0 stuff	2023-03-05 12:54:09 -08:00
Dillon Beliveau	33cd06ba91	oops	2023-03-05 12:47:07 -08:00
Dillon Beliveau	b4a9ec4c9c	handle consts more in mults and divs	2023-03-05 12:43:57 -08:00
Dillon Beliveau	0b6c26be4f	cleanup	2023-03-04 17:49:10 -08:00
Dillon Beliveau	78d96889e8	CMAKE_SYSTEM_PROCESSOR is AMD64 on 64 bit Windows	2023-03-04 17:48:58 -08:00
Dillon Beliveau	668b843f3e	dadd, daddu, dsub, dsubu, spilling fixes	2023-03-04 16:46:14 -08:00
Dillon Beliveau	18f37d593b	spilling fixes	2023-03-04 16:31:06 -08:00
Dillon Beliveau	b6d3f50bbc	trunc double->word	2023-03-04 16:07:46 -08:00
Dillon Beliveau	1c48d6f5ab	blezl, float lt compare, bc1t, bc1f, bc1fl	2023-03-04 16:02:08 -08:00
Dillon Beliveau	567da2fd81	handle spilled cond reg	2023-03-04 15:55:41 -08:00
Dillon Beliveau	7cf1094afb	mult	2023-03-04 15:55:32 -08:00
Dillon Beliveau	a3705f4186	subtraction with reg - imm	2023-03-04 15:38:23 -08:00
Dillon Beliveau	98aad3f509	fpu mov	2023-03-04 15:26:02 -08:00
Dillon Beliveau	29d5a5ef74	log block size in all cases	2023-03-04 15:25:31 -08:00
Dillon Beliveau	bf27db8ab2	fix NOT constant propagation, improve constant shrinking	2023-03-04 15:25:18 -08:00
Dillon Beliveau	baa75790ae	mult u32 reg reg	2023-03-04 14:38:19 -08:00
Dillon Beliveau	615c4adb84	better calculation of what instructions to put into a block	2023-03-04 14:31:06 -08:00
Dillon Beliveau	fd8539962a	trunc	2023-03-04 14:27:47 -08:00
Dillon Beliveau	9c4a97aa07	a few minor fixes	2023-03-04 14:27:28 -08:00
Dillon Beliveau	0d3dc5bb3f	mfc1	2023-03-01 00:49:41 -08:00
Dillon Beliveau	7fa0c7019f	convert float types with different modes	2023-03-01 00:44:51 -08:00
Dillon Beliveau	f268d956bf	float cmp, sub	2023-03-01 00:32:42 -08:00
Dillon Beliveau	06e58f7089	fix loading FGRs at the beginning of blocks	2023-03-01 00:32:22 -08:00
Dillon Beliveau	ba742d41da	compile float addition	2023-02-28 23:16:37 -08:00
Dillon Beliveau	2379544b5f	float constants	2023-02-28 23:11:16 -08:00
Dillon Beliveau	6d55d6ee8a	more stubs, implement float divides	2023-02-28 22:36:10 -08:00
Dillon Beliveau	7322b56a9d	determine type	2023-02-28 22:18:52 -08:00
Dillon Beliveau	8a6b355cbf	fixes, stub float subtraction	2023-02-28 22:17:50 -08:00
Dillon Beliveau	f4a02719e6	stub ir_float_check_condition, implement bc1tl	2023-02-28 22:04:18 -08:00
Dillon Beliveau	602b15e914	stub floating point divides and adds	2023-02-27 00:23:54 -08:00
Dillon Beliveau	0cc0b890e6	swc1, fix fgrs being reused for smaller values, emit cvt instructions	2023-02-26 18:02:13 -08:00
Dillon Beliveau	819659e510	LDC1, SDC1	2023-02-26 15:36:04 -08:00
Dillon Beliveau	5d155dbfb2	fix bug in register flushing	2023-02-26 15:35:46 -08:00
Dillon Beliveau	5ae2b28272	lwc1, cp1 cvt instructions	2023-02-26 15:06:51 -08:00
Dillon Beliveau	fd39ae898d	handle consts in mov_reg_type	2023-02-26 10:40:57 -08:00
Dillon Beliveau	13fb1d6edb	remove printfs	2023-02-25 18:36:20 -08:00
Dillon Beliveau	11dbb2be39	print_ir_block in header	2023-02-25 17:50:34 -08:00
Dillon Beliveau	380a9a1977	stub FPU IR emitters	2023-02-25 17:48:59 -08:00
Dillon Beliveau	71d406fd8c	fix warnings	2023-02-25 17:48:10 -08:00
Dillon Beliveau	94cf6af256	flush FPU registers	2023-02-25 17:30:29 -08:00
Dillon Beliveau	b442ea894a	allocate FPU registers	2023-02-24 17:45:59 -08:00