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Author SHA1 Message Date
Simon Eriksson 9316569eff pi: Fix PI DMA length alignment 
Fixes Yoshi's Story, F-1 World Grand Prix and probably many other games
 2021-03-09 22:20:12 +01:00
James Lambert deda9f9709 Have debugger handle memory exceptions 2021-03-08 20:17:17 +01:00
Simon Eriksson 27917c7df8 rsp: Fix VNOP and VNULL 2021-03-08 20:07:19 +01:00
Simon Eriksson 89e47d2968 Add Dinosaur Planet to cart DB 2021-02-20 18:39:05 +01:00
Simon Eriksson a54cbe042f si: Fix Memory Pak initialization 
Thanks to bryc for researching this issue and reviewing this fix
 2021-02-20 18:11:07 +01:00
Simon Eriksson 6f9f5784bf vr4300: Fix improper handling of valid bit in TLB probe function 
This fix restores GoldenEye support (#78)
 2021-02-19 23:42:00 +01:00
Tyler Stachecki 3f865dcedf
Merge pull request #187 from lambertjamesd/implement-gdb 
Implement gdb
 2021-01-11 17:58:54 -05:00
James Lambert 41116c3943 Document using gdb with cen64 2021-01-10 19:12:05 -07:00
James Lambert ee3d2fcc47 Implement gdb debugger 2021-01-10 17:07:29 -07:00
James Lambert 2865d107e4 Implement debugging hooks into vr4300 2021-01-10 17:07:21 -07:00
James Lambert 13720b1e29 Implement hash table 2021-01-10 17:05:35 -07:00
Tyler Stachecki b96c022e43
Merge pull request #186 from clbr/ri 
Implement Reserved Instruction exception
 2020-12-28 21:12:50 -05:00
Lauri Kasanen 55a46f45da Implement Reserved Instruction exception 2020-12-28 09:42:55 +02:00
Tyler Stachecki b9c36a4e7f
Merge pull request #184 from clbr/fpu 
Implement fpu prid
 2020-12-27 12:42:33 -05:00
Tyler Stachecki 814c272ca4
Merge pull request #159 from lambertjamesd/implement-trap-instructions 
Implement trap instructions
 2020-12-27 12:41:58 -05:00
James Lambert ee9cd6f0da Add correct INFO to trap macros 
Correctly annotate unused parameters in trap functions
 2020-12-27 10:30:26 -07:00
Lauri Kasanen 1369c191a2 Implement fpu prid 2020-12-27 09:30:20 +02:00
Tyler Stachecki ed6462e365
Merge pull request #178 from clbr/profiler 
Teach the profiler about L1D misses
 2020-12-26 10:44:52 -05:00
Lauri Kasanen 4316ecd0dd Implement cp0 prid 2020-12-23 16:09:12 +01:00
Lauri Kasanen 81bf10960f Teach the profiler about L1D misses 2020-12-21 19:05:07 +02:00
Lauri Kasanen 9464379f8a rsp: Remove small IO writes RMW, hw does not do that 2020-12-21 16:28:53 +01:00
Tim Gates 2abc63d78a docs: fix simple typo, accesssor -> accessor 
There is a small typo in bus/controller.h.

Should read `accessor` rather than `accesssor`.
 2020-12-21 16:28:33 +01:00
James Lambert 054bcb90f7 Implement trap instructions 2020-09-05 17:46:10 -06:00
Simon Eriksson a109ac02de Cart DB updates 2020-05-31 20:55:02 +02:00
Simon Eriksson e340a74a26 rsp: Remove copy-paste leftover from LTV/STV code 2020-05-31 20:25:26 +02:00
Mike Ryan 736220010d
Merge pull request #152 from hcs64/clear-halt-save-pc 
Preserve SP PC when clearing halt, don't re-init pipeline if not halted
 2020-05-30 06:55:51 -07:00
Adam Gashlin 0c40ffdde2 Preserve SP PC when clearing halt 
Also don't re-init pipeline if SP wasn't already halted.

Fixes #151
 2020-05-29 23:49:32 -07:00
Simon Eriksson ec94eef39b
Merge pull request #142 from MIPT-ILab/develop 
Update Travis images
 2020-05-28 21:46:58 +02:00
Simon Eriksson 1176dae84a
Merge pull request #144 from MIPT-ILab/ubsan 
Pass UB sanitizer flags to linker
 2020-05-28 21:41:21 +02:00
Mike Ryan 15cf44f36f
Merge pull request #150 from sp1187/brpt 
vr4300: Implement break instruction
 2020-05-27 14:41:16 -07:00
Simon Eriksson fa73cbe0fe vr4300: Implement break instruction 2020-05-27 23:00:53 +02:00
Simon Eriksson fe81d08ca2 Remove unused global bus pointer variables 2020-05-15 21:28:24 +02:00
PeterLemon 94f1121cb3
Merge pull request #145 from sp1187/transpose 
Basic RSP LTV/STV support
 2020-04-15 07:23:03 +01:00
Simon Eriksson b08188f388 Basic RSP LTV/STV support 2020-04-15 07:38:09 +02:00
Pavel Kryukov 5d7acbd94c Pass UB sanitizer flags to linker 2020-03-27 23:53:49 +03:00
Simon Eriksson 50be16a0ef
Merge pull request #141 from pavelkryukov/patch-1 
Define _DEFAULT_SOURCE
 2020-03-26 22:41:32 +01:00
Pavel I. Kryukov f67a25a651 Update Travis images 2020-03-27 00:19:16 +03:00
Pavel I. Kryukov 8deed1f7b2
Define _DEFAULT_SOURCE 2020-03-27 00:15:55 +03:00
Simon Eriksson e9f54ae139
Merge pull request #71 from queueRAM/audio 
Don't make any OpenAL calls if -noaudio option is used.
 2020-03-26 20:03:48 +01:00
Jason Benaim b6466b5ecf
Merge pull request #127 from joeldipops/master 
Implemented MBC1/MBC2/MBC5 bank switching in transfer pak code
 2020-01-26 14:07:40 -08:00
Simon Eriksson 7f2eb66a74
Merge pull request #137 from MIPT-ILab/mi 
Use typed pointer for MI interfaces of VR4300
 2019-12-14 16:33:00 +01:00
Pavel I. Kryukov 29d6d12339 Use typed pointer for MI interfaces of VR4300 2019-12-09 22:38:17 +03:00
joeldipops cbfbe5018c improved calculation of rom_size from code as per review comment 2019-11-04 21:34:58 +10:00
Nabile Rahmani 05eedd91b5 DMTC0 status writes should update the segmented memory. (#135) 
This matches the MTC0 code.
 2019-11-03 17:46:58 +01:00
Nabile Rahmani 30f17b2e20 PI: name constants and fixed DMA/reset controller behaviour (#134) 
* PI: name constants and fixed DMA/reset controller behaviour.

When a reset controller request is performed, only busy and error bits are cleared.
When DMAs begin, the DMA busy bit is set, but the interrupt bit shouldn't be touched yet.

* Ignore PI register write and flag error when busy.
 2019-11-03 17:46:44 +01:00
Nabile Rahmani fd4cb9be51 Clear the frame buffer to avoid garbage. (#133) 
Some graphics stacks just suck (like AMD + Mesa), so we have to clear the frame buffer on each frame, otherwise garbage and/or flickering appears on undrawn areas.
Fixes #53.
 2019-11-03 17:46:09 +01:00
Jason Benaim 607dc12ecf PROT_EXEC doesn't make sense in mmap flags. Fixes #128. 2019-07-28 19:03:49 -07:00
Jason Benaim 118e6331ff
Merge pull request #129 from larb0b/master 
device/sha1.c: Remove sys/cdefs.h include
 2019-07-26 23:22:26 -07:00
Larkin Nickle 909db0eaf2 device/sha1.c: Remove sys/cdefs.h include 2019-07-27 01:52:11 -04:00
joeldipops 47fa885d13 mbc2 added and ram enable bug fixed 2019-07-24 22:03:17 +10:00