Commit graph

909 commits

Author SHA1 Message Date
Tyler J. Stachecki 8aff451c4b Partially fix Windows builds. 2017-03-19 02:27:53 +00:00
Tyler J. Stachecki b9e6d10341 Add macOS cross-build support. 2017-03-18 22:16:35 -04:00
Tyler J. Stachecki 82c2424c44 Fix macOS builds. 2017-03-18 22:11:42 -04:00
Mike Ryan 07301222dd build: add FindIconv cmake file
Forgot to add this file in previous commit. See #59.
2017-03-08 10:18:35 -08:00
Mike Ryan 8d0e7bb627 pi: add support for IS Viewer 64
When -is-viewer is passed on the command line, create an IS Viewer
object that intercepts writes at 0x13FF0000. This is used by Ocarina of
Time Master Quest Debug to log debug messages.

The messages are encoded in EUC-JP, so we bring in iconv to convert that
to UTF-8 so the messages can be printed to modern consoles.

Props to jrra (@jkbenaim) and spinout for reverse engineering the
interface and documenting it: http://wiki.spinout182.com/w/IS64
2017-02-28 19:55:55 -08:00
Tyler J. Stachecki ac8f2283af Use a different version of cpuid functions. 2017-02-15 19:04:53 -05:00
Snowstorm64 e5061351a9 n64video.c: Sync up to r107.
(angrylion) rdp: fixed the interaction between x-scissoring and
the "texel 1" combiner input in one-cycle mode; fixed a bug in
x-scissoring that could occur when a coordinate was compared with
XH of the scissoring box (both bugfixes confirmed by a test rom).
2017-02-15 18:38:28 -05:00
Snowstorm64 e3a4ac04b9 n64video.c: Sync up to r106.
(angrylion) rdp: more accurate emulation of one-cycle LOD for the
final pixels of a span (based on hardware tests); some LOD
microoptimizations.
2017-02-15 18:38:28 -05:00
Snowstorm64 9e67a78b44 n64video.c: Sync up to r105.
(angrylion) rdp: fixed reads from the TMEM when the t coordinate is
greater than 0xff (confirmed by a test rom)
2017-02-15 18:38:28 -05:00
Snowstorm64 5ed1a9213e n64video.c: Sync up to r104.
(angrylion) rdp: fixed a bug in texture coordinate clamping (confirmed
by a test rom)
2017-02-15 18:38:28 -05:00
Snowstorm64 ad8c3f07ca n64video.c: Sync up to r103.
(angrylion) rdp: fixed a bug in the edgewalker, the distributive law
doesn't work here because of integer overflow (confirmed by a test rom)
2017-02-15 18:38:28 -05:00
Snowstorm64 36dcfdb932 n64video.c: Sync up to r102, skipping r101 (VI
emulation related)

(angrylion) rdp: fixed how the unscissored-major-x coordinate of a span
is processed (confirmed by a new test rom)
2017-02-15 18:38:28 -05:00
Snowstorm64 45f59e2ae2 n64video.c: Sync up to r100.
(angrylion) rdp: quick follow-up to r99
2017-02-15 18:38:28 -05:00
Snowstorm64 b592cf492c n64video.c: Sync up to r99, VI changes are skipped.
(angrylion) rdp: new approach to interlaced mode emulation, based on
improved understanding. Most interlaced mode games should look correct
with most emulators now. Removed a redundant sign-extension used on YUV
texels (idea by LegendOfDragoon, thanks). Minor refactoring.
2017-02-15 18:38:28 -05:00
Mike Ryan 367b77b134 build: build Release with Debug Info by default
We want builds to be fast out of the box, so this option will build a
Release binary using a default cmake configuation.
2017-02-14 20:38:46 -08:00
Mike Ryan d5dde96ecf build: enable VR4300 busy wait by default
This option increases performance without impacting emulation accuracy.
2017-02-14 20:38:46 -08:00
Mike Ryan 1a14936b4b build: reorder CPU extensions from newest to oldest, and change default
CPU extensions were previously ordered from oldest to newest, with
oldest (SSE2) being selected by default. This could cause poor
performance for less savvy users. Instead we use Native by default,
which will use the best available for the detected CPU, and list them in
descending order. If the compiled binary uses extensions not available
on the host CPU, the core will throw an error so user experience is not
significantly degraded.

See #56
2017-02-14 20:38:46 -08:00
Mike Ryan 6acc6931ee core: detect CPU extensions at runtime and throw warning/error
If cen64 is compiled with CPU extensions not supported by the running
CPU, throw an error. If the code is compiled with older extensions but
the running CPU supports faster ones, throw a warning.
2017-02-14 20:11:57 -08:00
Mike Ryan abca698a75 core: add cpuid fetching code from 4996031 2017-02-14 16:44:18 -08:00
Tyler Stachecki dcefa18582 Merge pull request #50 from sp1187/cic
si: Add support for 7102 CIC.
2016-10-21 10:19:08 -04:00
Simon Eriksson 51cd3eec1e si: Add support for 7102 CIC.
Fixes Lylat Wars (PAL).
2016-10-21 16:02:54 +02:00
Tyler J. Stachecki 0d0e042817 vr4300/cp0: @sp1187: Fix undefined CP0 register access.
simer/sp1187 pointed out that undefined CP0 registers all
share a common value (that is, a write to any undefined CP0
register effectively acts as a write to *all* undefined CP0
registers).

This commit implements the specified behaviour.
2016-10-19 12:10:44 -04:00
Tyler J. Stachecki 6f6f7698e7 vi: Handle (non-)interlaced modes better.
I accidentally flipped the logic for a bit; if the LSB of
VI_V_SYNC_REG is clear, then interlaced mode is enabled and
vise-versa.
2016-10-18 23:14:22 -04:00
Tyler Stachecki 4564751193 Merge pull request #48 from sp1187/rspcp0
rsp: Ignore highest bit of RSP CP0 register number.
2016-10-08 15:46:24 -04:00
Simon Eriksson 35f15f8db4 rsp: Ignore highest bit of RSP CP0 register number. 2016-10-08 20:56:26 +02:00
Jason 1c518539c2 Add note about debugger not existing 2016-08-31 21:45:04 -04:00
Jason 6cd0777286 Fix -debug argument parsing 2016-08-31 21:44:58 -04:00
Mike Ryan 36a4a6fdfa dd: identify IPL and add support for all known dumped IPLs
This also fixes a regression introduced in 3900be4 that prevented the DD
IPL from booting.
2016-08-31 18:33:15 -07:00
Tyler J. Stachecki 156d592abb rsp: Bugfix for SSE2 RSP.
Thanks to Tiny Tiger and AIO for helping to point this out.
One of the arguments was being overwritten before it was
used, which caused an issue with the SSE2 codepath (while
the SSE4.1 one was fine).
2016-08-06 20:53:04 -04:00
Tyler J. Stachecki 3900be4776 bus: Perform open bus reads for unmapped addresses.
Fixes F-Zero X (cartridge version).
2016-07-17 20:47:07 -04:00
Tyler J. Stachecki d8f264eb09 vi: Make VI emulation less bad.
Somewhere in the world, somebody with more knowledge than
I is probably screaming about how wrong this NTSC signal
stuff is, but it's at least less worse than what was there
before!

The way interlaced signals are handled is still VERY wrong
(I need to swizzle in the lines from each field before
shipping a framebuffer off to the GPU).

That being said, some ROMs like LaC fire demo and one of
SonCrap's demos look correct now (there is no flickering).
2016-07-17 20:14:01 -04:00
Tyler J. Stachecki 304d711414 ai: Fix regression in previous commit. 2016-07-10 15:39:42 -04:00
Tyler J. Stachecki 5f5a0005a6 ai: Revamp the audio system.
This is sloppy patchwork, but it's better sloppy patchwork
than the previous sloppy patchwork! Will need to resample
the audio and work with flucutations in subframe timing to
solve the rest of the popping.
2016-07-10 14:23:20 -04:00
Tyler Stachecki b808fe50e0 rsp: Qualify shuffle arrays as static. 2016-07-09 20:00:33 -04:00
Tyler Stachecki 1e86268eee rsp: Fix SQV and SRV (more endianness issues). 2016-07-09 19:38:26 -04:00
Tyler Stachecki ab2c932aaf rsp: Fix SP->RDRAM stride bug.
krom spotted this one using his upcoming GB emulator.
2016-07-09 19:01:45 -04:00
Tyler Stachecki 55e64a6c27 rsp: Fix LRV bug (data shifting problem).
tl;dr: Using LUTs to shift and byteswap all in one x86
instruction is awesome for performance, but makes things
absolutely horrendous to debug.

With this commit, audio mixing on the RSP works properly.
2016-07-09 17:49:03 -04:00
Tyler Stachecki 1e47020ccc rsp: Fix LQV bug (related to endianness). 2016-07-09 16:24:40 -04:00
Tyler Stachecki 1e20e171a8 rsp: Fix LPV bug (more endianness issues). 2016-07-09 16:17:36 -04:00
Tyler Stachecki cae6b6de78 rsp: Fix LBV bug (related to endianness). 2016-07-09 16:14:27 -04:00
Tyler Stachecki 6d3cd1e0d0 rsp: Fix link PC result (12th bit should not get set). 2016-07-09 13:30:05 -04:00
Tyler J. Stachecki 5a21c4c7d5 vr4300: Fix a major TLB bug.
I seriously screwed up the TLB lookup logic so bad that
only the first 8 TLB entries were being probed. Fix that.

This fixes (at least) Paper Mario and Mario Tennis.
2016-07-09 14:49:59 -04:00
Tyler J. Stachecki a12c5a3e04 vr4300: Fix a bug in (D) Index Load Tag.
The VALID and DIRTY bits were not being shifted into the
proper positions after reading them from the line states.
2016-07-09 12:39:45 -04:00
Tyler J. Stachecki 9886ec2587 vr4300: Fix a (fairly serious) cache bug.
The action taken for (D) Index_Write_Back_Invalidate was
wrong. As it turns out, the VR4300 manual has an extremely
serious typo in the operation section.

According to the manual, this cache operation should use
the virtual address to index a block (line) in the cache.
If that line is not in the INVALID state, it should be
unconditionally flushed out to memory and the line should
then be invalidated.

The hardware, however, seems to only write back the block
(line) in the event that the line is VALID and DIRTY. It
does, however, invalidate the line regardless of whether
or not the line was DIRTY. That is to say, CLEAN lines get
invalidated as well.

This commit fixes the erroneous behavior.
2016-07-09 12:12:15 -04:00
Tyler J. Stachecki c85def363c Fix a bug in the recent CTC2 impl. 2016-06-30 10:05:11 -04:00
Tyler Stachecki 91b18f2644 rsp: Implement CTC2. 2016-06-29 21:38:25 -04:00
Tyler J. Stachecki 91926630e8 Fix non-Windows builds. 2016-06-29 20:21:31 -04:00
Tyler J. Stachecki c1d381e729 Last MSVC build fix.
With this, MSVC builds should now work.
2016-06-26 17:38:52 -04:00
Tyler J. Stachecki 9492bba954 Another MSVC build fix. 2016-06-26 17:23:48 -04:00
Tyler J. Stachecki ec475c6874 openal: Kill audio if ai_init fails. 2016-06-26 17:20:32 -04:00