(angrylion) rdp: fixed the interaction between x-scissoring and
the "texel 1" combiner input in one-cycle mode; fixed a bug in
x-scissoring that could occur when a coordinate was compared with
XH of the scissoring box (both bugfixes confirmed by a test rom).
(angrylion) rdp: new approach to interlaced mode emulation, based on
improved understanding. Most interlaced mode games should look correct
with most emulators now. Removed a redundant sign-extension used on YUV
texels (idea by LegendOfDragoon, thanks). Minor refactoring.
CPU extensions were previously ordered from oldest to newest, with
oldest (SSE2) being selected by default. This could cause poor
performance for less savvy users. Instead we use Native by default,
which will use the best available for the detected CPU, and list them in
descending order. If the compiled binary uses extensions not available
on the host CPU, the core will throw an error so user experience is not
significantly degraded.
See #56
If cen64 is compiled with CPU extensions not supported by the running
CPU, throw an error. If the code is compiled with older extensions but
the running CPU supports faster ones, throw a warning.
simer/sp1187 pointed out that undefined CP0 registers all
share a common value (that is, a write to any undefined CP0
register effectively acts as a write to *all* undefined CP0
registers).
This commit implements the specified behaviour.
Thanks to Tiny Tiger and AIO for helping to point this out.
One of the arguments was being overwritten before it was
used, which caused an issue with the SSE2 codepath (while
the SSE4.1 one was fine).
Somewhere in the world, somebody with more knowledge than
I is probably screaming about how wrong this NTSC signal
stuff is, but it's at least less worse than what was there
before!
The way interlaced signals are handled is still VERY wrong
(I need to swizzle in the lines from each field before
shipping a framebuffer off to the GPU).
That being said, some ROMs like LaC fire demo and one of
SonCrap's demos look correct now (there is no flickering).
This is sloppy patchwork, but it's better sloppy patchwork
than the previous sloppy patchwork! Will need to resample
the audio and work with flucutations in subframe timing to
solve the rest of the popping.
tl;dr: Using LUTs to shift and byteswap all in one x86
instruction is awesome for performance, but makes things
absolutely horrendous to debug.
With this commit, audio mixing on the RSP works properly.
I seriously screwed up the TLB lookup logic so bad that
only the first 8 TLB entries were being probed. Fix that.
This fixes (at least) Paper Mario and Mario Tennis.
The action taken for (D) Index_Write_Back_Invalidate was
wrong. As it turns out, the VR4300 manual has an extremely
serious typo in the operation section.
According to the manual, this cache operation should use
the virtual address to index a block (line) in the cache.
If that line is not in the INVALID state, it should be
unconditionally flushed out to memory and the line should
then be invalidated.
The hardware, however, seems to only write back the block
(line) in the event that the line is VALID and DIRTY. It
does, however, invalidate the line regardless of whether
or not the line was DIRTY. That is to say, CLEAN lines get
invalidated as well.
This commit fixes the erroneous behavior.
Originally these functions were intended to workaround
problems experienced by RSP vector register caching,
but we don't use it anymore so we can just nix them.
Fixes#41
Add a "running" boolean to the master device struct, and set it to false
when the main window is closed. All the tight inner while (1) loops now
become while (running).
Closes#24
