Commit graph

18317 commits

Author SHA1 Message Date
Lee Leahy
db54acd1aa UPSTREAM: util/checklist: Place tables in proper boot order
during the boot, romstage occurs before postchar which is before
ramstage.  Place the tables in the proper boot order when generating
the final webpage.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I5df3ceb797aced58fe5ea3d10d78254a27341e47
Reviewed-on: https://chromium-review.googlesource.com/368024
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11 03:14:32 -07:00
Lee Leahy
9828882b43 UPSTREAM: util/checklist: Concatinate optional list to complete list
Don't require that the routines in the .optional file be listed in the
.complete data file.  Concatinate the two files when building the
complete symbol list.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16037
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I596134e1a19311d357aa0d93cfb33c7ca9801e2e
Reviewed-on: https://chromium-review.googlesource.com/368023
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11 03:14:30 -07:00
Lee Leahy
c5908c049e UPSTREAM: util/checklist: Process .debug files before .elf files
Ensure that the output file is created by processing the .debug files
before the .elf files.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ief8d774249c9d8eb313f3d10f04d7e4f2e3cf491
Reviewed-on: https://chromium-review.googlesource.com/368022
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11 03:14:27 -07:00
Lee Leahy
52277458a8 UPSTREAM: util/checklist: Add usage instructions
Document how to use the checklist and how to generate the data files.

TEST=Build and run on Amenia

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Idffc0683e916cbc5a984028886dc3d89a01d0595
Reviewed-on: https://chromium-review.googlesource.com/368021
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11 03:14:25 -07:00
Julius Werner
8c3b74fb21 chromeos: Make CHROMEOS_RAMOOPS_NON_ACPI a default for non-ACPI boards
This patch enables the CHROMEOS_RAMOOPS_NON_APCI Kconfig option as a
default across all non-x86 Chrome OS boards.

CQ-DEPEND=CL:367905
BRANCH=None
BUG=None
TEST=See depthcharge CL.

Change-Id: I16ff7f68762a995cd38e5fddaf6971d4b9f07e21
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10 22:16:49 -07:00
Julius Werner
103d86e68c Revert "gru: Show the current time on start-up"
This reverts commit d0361193e0.

google_chromeec_init() is a weird function that can lead to confusing
behavior. I'm not sure how it's meant to work on the boards that use it,
but it causes problems on Kevin and other non-x86 boards have never used
it either. It doesn't really do anything anyway (the EC works fine
without an initial HELLO), so at best it's just a waste of time... let's
take it back out.

There's also no need to display the current time on every boot... other
boards don't do that and the eventlog already fills the same purpose.
Cut it out to avoid one extra host command overhead.

BRANCH=None
BUG=chrome-os-partner:55995
TEST=Recovery reasons now get correctly propagated across the EC reboot.

Change-Id: I58fd5e6094e1c8cb6368e7a4569ab9231375fbc9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367351
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Shelley Chen <shchen@chromium.org>
2016-08-10 20:07:34 -07:00
Lee Leahy
cc45880160 UPSTREAM: mainboard/intel/galileo: Add FSP 2.0 Kconfig support
Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0
builds for Quark.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I715f8117d2a68361d634c67cc4d73742e474c635
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15864
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367395
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:07:05 -07:00
Lee Leahy
3935b5f173 UPSTREAM: soc/intel/quark: Add header files for FSP 2.0
Add the FSP 2.0 header files for Quark.  These files were run through
the drivers/intel/fsp2_0/header_util to convert the data types so that
they are compatible with the coreboot build system.

TEST=Build and run on Galileo Gen2.

BUG=None
BRANCH=None

Change-Id: Ic386da82a12feefda555f6722c7e7bf19740877a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15863
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367394
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:07:03 -07:00
Lee Leahy
2dca83717b UPSTREAM: soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: Id56edcf7c9336f3778b3fdbddab8775f5d5974e6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367393
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:07:00 -07:00
Lee Leahy
c75a096c3d UPSTREAM: soc/intel/quark: Initialize MTRRs in bootblock
Initialize the MTRRs for use by bootblock and romstage.
Display the MTRRs.

TEST=Build and run on Galileo Gen2.

BUG=None
BRANCH=None

Change-Id: Iaa51daf2784d5e203c3b937038bad91dcb74a48c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15861
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367392
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:58 -07:00
Lee Leahy
6702972cdb UPSTREAM: soc/intel/quark: Remove use of EDK-II macros and data types
Include assert.h to use coreboot's ASSERT macro.
Replace the use of UINT32 data type with uint32_t.
Replace the use of UINT8 data type with uint8_t.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I9e727d5180fb8f1e6e5a13696fe2c6f391193c38
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15858
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367391
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:56 -07:00
Werner Zeh
a0c09b89b5 UPSTREAM: fsp_broadwell_de: Add DMAR table to ACPI
Create DMAR table for Broadwell-DE SoC.

TEST=Booted MC BDX1 into lubuntu15, dumped ACPI tables with acpidump and
     disassembled DMAR table using iasl. The table contents are as
     expected and the kernel loads DMAR table without errors.

BUG=None
BRANCH=None

Change-Id: Id08f8bdb3d998796a3828604eae5f6b02f5cd7dc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15913
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/367390
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:53 -07:00
Nico Huber
8af6568ddd UPSTREAM: cbfstool: Check for excessive arguments
BUG=None
BRANCH=None
TEST=None

Change-Id: Iad198c957d171389dc3454f15dd0ad743425354d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16019
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/367389
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:51 -07:00
Nico Huber
33498a03ff UPSTREAM: cbfstool: Check arguments to strtoul() where appropriate
The interface to strtoul() is a weird mess. It may or may not set errno
if no conversion is done. So check for empty strings and trailing
characters.

BUG=None
BRANCH=None
TEST=None

Change-Id: I5523109ab5054c49ea08887b98b40899da809190
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16012
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367388
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:49 -07:00
Nico Huber
03fecd49f9 UPSTREAM: Makefile.inc: Strip output of wc
Apparently BSD's wc indents its output.

BUG=None
BRANCH=None
TEST=None

Change-Id: I47076e455f529c1b0d819b821eca09a78648e97c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16013
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/367387
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:46 -07:00
Werner Zeh
2d735f690c UPSTREAM: ACPI: Add code to create root port entry in DMAR table
PCI root ports with "Address Translation Service" capability can be
reported in DMAR table in the ATSR scope to let the OS know how to
handle these devices the right way when VT-d is used.
Add code to create an entry for a PCI root port using the type
"SCOPE_PCI_SUB".

BUG=None
BRANCH=None
TEST=None

Change-Id: Ia73f174f9546e6d622ede37f4b6264380972678e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15912
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/367386
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:44 -07:00
Werner Zeh
f28c09b1a5 UPSTREAM: ACPI: Add code to include ATSR structure in DMAR table
DMAR tables can contain so called "Address Translation Service Reporting"
(ATSR) structure. It is applicable for platforms that support
Device-TLBs and describe PCI root ports that have this ability.
Add code to create this ATSR structure.

In addition, a function to fix up the size of the ATSR
structure is added as this is a new type and using the function
acpi_dmar_drhd_fixup() can lead to confusion.

BUG=None
BRANCH=None
TEST=None

Change-Id: I165e1441a5f20af35189a0b3ffca6f98b69df87a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15911
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/367385
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:42 -07:00
Lee Leahy
6e94cdbd09 UPSTREAM: mainboard/intel/galileo: Remove use of EDK-II macros & data types
Add assert.h to use coreboot's ASSERT macro.
Replace the use of UINT8 data type with uint8_t.

TEST=Build and run on Galileo Gen2.

BUG=None
BRANCH=None

Change-Id: Ibc0180272cbfd7df4928bd841b02e23562fe1223
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15859
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367384
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:39 -07:00
Lee Leahy
b5b1e3df96 UPSTREAM: soc/intel/quark: Make ramstage relocatable
Relocate ramstage into CBMEM.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: Ic8218ae3f173091b78bc722d6d4e11c24cae0742
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15994
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/367383
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 20:06:37 -07:00
Shunqian Zheng
5707d1269a Revert "rockchip: rk3399: enable sdhci clk for emmc"
This reverts commit d3b45f6b05 ("rockchip: rk3399: enable sdhci clk
for emmc")

BUG=chrome-os-partner:52873
TEST=boot from usb/sdcard and check there is /dev/mmcblk0
BRANCH=none

Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/367421
Commit-Ready: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-08-10 13:09:47 -07:00
Lee Leahy
f169a13839 UPSTREAM: drivers/intel/fsp2_0: Update the debug levels
Choose appropriate debug levels for the various messages in the FSP
driver.  Change:

* BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows
  builder to disable FSP driver output by selecting
  CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7

* BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the
  payload from successfully booting

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I36f5ba6e2a0e89b7c1127218b982a105039e90a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16003
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367382
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:34 -07:00
Lee Leahy
4772fd1c23 UPSTREAM: drivers/intel/fsp2_0: Remove fsp_print_upd_info declaration
Remove unused function declaration.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I0c0cb14e636f037143157b9b85e53ce126cfbe9f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367381
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:32 -07:00
Lee Leahy
69be7ba3c4 UPSTREAM: drivers/intel/fsp2_0: Disable display of FSP header
Add a Kconfig value to enable display of FSP header.  Move the display
code into a separate module to remove it entirely from the final image.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I55e44c37f42576df5096f0617fdc43941a330125
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16002
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367380
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:30 -07:00
Lee Leahy
3415952259 UPSTREAM: drivers/intel/fsp2_0: Handle FspNotify calls
Other SOC platforms need to handle the FspNotify calls in the same way
as Apollo Lake.  Migrate the FspNotify calls into the FSP 2.0 driver.
Provide a platform callback to handle anything else that needs to be
done after the FspNotify call.

Display the MTRRs before the first call to fsp_notify.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I9a8dfd3d7eb3a51f9a1028b3ea4f3eeaa290857f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367379
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:27 -07:00
Lee Leahy
701842a69c UPSTREAM: drivers/intel/fsp2_0: FSP driver handles all FSP errors
Move all FSP error handling into the FSP 2.0 driver.  This removes the
need to implement error handling within the SOC code.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I6e1a768379944353c25ce2ee69f94d655028a411
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15853
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367378
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:25 -07:00
Lee Leahy
f92e8cee6c UPSTREAM: drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit
Verify that FSP is properly returning:
* HOB list pointer
* FSP_BOOTLOADER_TOLUM_HOB
* FSP_RESERVED_MEMORY_RESOURCE_HOB

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: Ia8b9c8caade098fc583d8757df55a301f16b5715
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15850
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367377
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:23 -07:00
Lee Leahy
bac1b1a612 UPSTREAM: drivers/intel/fsp2_0: Add display HOB support
Add support to display the HOBs returned by FSP:
* Add Kconfig value to enable HOB display
* Move hob_header, hob_resource and uuid_name structures into util.h
* Move hob_type enum into util.h
* Remove static from the debug utility functions
* Add fsp_ prefix to the debug utility functions
* Declare the debug utility functions in debug.h
* Add HOB type name table
* Add more GUID values
* Add new GUID name table for additional GUIDs
* Add routine to convert EDK-II GUID into a name
* Add SOC specific routine to handle unknown GUID types
* Add routine to convert HOB type into a name
* Add SOC specific routine to handle unknown HOB types
* Add routine to display the hobs

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: If23692aa426606fe49018d06f358933b3ecd558a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15851
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367376
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:20 -07:00
Lee Leahy
b569403592 UPSTREAM: drivers/intel/fsp2_0: Add UPD display support
Add UPD display support:
*  Add a Kconfig value to enable UPD value display
*  Add a routine to display a UPD value
*  Add a call before MemoryInit to display the UPD parameters
*  Add a routine to display the architectural parameters for MemoryInit
*  Add a weak routine to display the other UPD parameters for MemoryInit
*  Add a call before SiliconInit to display the UPD parameters
*  Add a weak routine to display the UPD parameters for SiliconInit

TEST=Build and run on Galileo Gen2.

BUG=None
BRANCH=None

Change-Id: I651a56d57d635c682f206590d8d86854c7b4de24
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15847
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367375
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 00:27:40 -07:00
Lee Leahy
14d37b9cac UPSTREAM: drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
Display the MTRR values in the following locations:
* Before the call to FspMemoryInit to document coreboot settings
* After the call to FspMemoryInit
* Before the call to FspSiliconInit
* After the call to FspSiliconInit
* After the call to FspNotify
* Before the call to FspNotify added in patch 15855

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: If3e99ec06c9df45e6185e33acc843b29630899ff
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15849
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367374
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 00:27:38 -07:00
Jonathan Neuschäfer
e7a39c6953 UPSTREAM: arch/riscv: Add include/arch/barrier.h
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
It is currently provided by atomic.h, but I think it fits better into
barrier.h.

The "fence" instruction represents a full memory fence, as opposed to
variants such as "fence r, rw" which represent a partial fence. An
operating system might want to use precisely the right fence, but
coreboot doesn't need this level of performance at the cost of
simplicity.

BUG=None
BRANCH=None
TEST=None

Change-Id: I415c642941471bc3bf99bfeeb235cfaef7e247fe
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15830
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/367373
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 00:27:36 -07:00
Antonello Dettori
498622cbad UPSTREAM: libpayload: split "Drivers" config section in Kconfig
Move the configuration of the timer, storage and USB drivers from the
main Kconfig to three separate ones stored in the respective
directories.

This reduces the LOC of Kconfig and makes it more manageable.

BUG=None
BRANCH=None
TEST=None

Change-Id: Iab88c135c3dc5d2e4a9859ecdab31bbb70b699b8
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15914
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/367372
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 00:27:33 -07:00
jiazi Yang
9506c4c07e chromeec/acpi: add Tablet event and EC ACPI MEM
Switch DPTF table when TABLET/NOTEBOOK mode changes
1. EC send EC_HOST_EVENT_MODE_CHANGE(29/0x1D) when mode changes
2. Host read current "physical mode" from EC ERAM

BUG=chrome-os-partner:53526
BRANCH=master
TEST=build glados

Change-Id: I5a3363ff9c958decb5aed1c85fc2a1ef6670931d
Signed-off-by: jiazi Yang <Tomato_Yang@asus.com>
Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Signed-off-by: jiazi Yang <Tomato_Yang@asus.com>
Reviewed-on: https://chromium-review.googlesource.com/365991
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-09 22:10:53 -07:00
Martin Roth
fd8a5a1b1e UPSTREAM: google/lars & intel/kunimitsu: Disable EC build
The Chrome EC codebase no longer supports the google/lars and
intel/kunimitsu boards.  Disable the build in those platforms.

BUG=None
BRANCH=None
TEST=None

Change-Id: I42334ccc33dae3ab2bd65cb68aece44f0a504f50
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15869
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/367371
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:35 -07:00
Fabian Kunkel
315445d5a2 UPSTREAM: superio/fintek/f81866d: Add support for UART 3/4
Pins for UART 3/4 are by default GPIO pins.
This patch sets the pins in UART mode.
Since UART 1/3 and 2/4 share the same interrupt line,
the patch needs to enable also shared interrupts.
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html

BUG=None
BRANCH=None
TEST=None

Change-Id: Ie6c70544eb115114d83d99bed34609fc3217a6b8
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15564
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/367370
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:33 -07:00
Martin Roth
4e0f8ec920 UPSTREAM: util/lint: Add a lint tool to find non-ascii & unprintable chars
This examines characters in coreboot's sourcecode to look for values
that are not TAB, or in the range of space (0x20) to ~ (0x7F).

It specifically excludes copyright lines so that names with high-
ASCII characters are not flagged.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ia4fde98fc91f90fb693129fe26527fe580563745
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15979
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367369
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:31 -07:00
Kane Chen
32ba092043 UPSTREAM: google/reef: Add pull up 20K for LPC SERIRQ
per hw team's check and info from EDS, this pin needs to be pu 20K.
Otherwise SoC may not notice interrupt request from
EC over LPC because SERIRQ line is floating.

BUG=chrome-os-partner:55586
BRANCH=none
TEST=boot ok and Quanta factory verified the keyboard issue is gone

Change-Id: I33700d2d7e3377b4dd8244f787a383e1622f9a7d
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/15951
Tested-by: build bot (Jenkins)
Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/367368
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:28 -07:00
Shankar, Vaibhav
097712c8f2 UPSTREAM: intel/amenia: Add GPIO changes to assert SLP_S0/Reset signal
PMIC/PMU: Set the iosstates for PMIC to assert the reset
signal, PMU to assert SLP_S0 signal.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ieae0e1a35ddde020f1bceedc26fa6d4d5700f861
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/15777
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367367
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:26 -07:00
Shankar, Vaibhav
23c8b2499d UPSTREAM: soc/intel/apollolake: Add iosstate macros for GPIO
IO Standby State (IOSSTATE): The I/O Standby State defines
which state the pad should be parked in when the I/O is in a
standby state. Iosstate set to 15 means IO-Standby is ignored
for this pin (same as functional mode), So that pin keeps on
functioning in S3/S0iX.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ic1e79ea1416440acb913761e7624d59781e0b2c6
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/15776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367366
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:24 -07:00
Furquan Shaikh
39dce8716c UPSTREAM: drivers/fsp2_0: Increment boot count for non-S3 boot
If ELOG_BOOT_COUNT is enabled and the boot is not s3 resume, then
increment boot count.

BUG=chrome-os-partner:55473
BRANCH=None
TEST=None

Change-Id: Ie14a359677cc6cf933c553632114eb43beae1a80
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15948
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/367365
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:21 -07:00
Furquan Shaikh
9c84cbdfe8 UPSTREAM: intel/apollolake: Enable upper CMOS bank in bootblock
Upper CMOS bank is used to store the boot count. It is important to
enable it as soon as possible in bootblock.

BUG=chrome-os-partner:55473
BRANCH=None
TEST=None

Change-Id: Iaa8b8613687c9d99d02c17be61d13c1285113132
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15998
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/367364
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:19 -07:00
Furquan Shaikh
c282ad3dee UPSTREAM: elog: Include declarations for boot count functions unconditionally
There is no need to add guards around boot_count_* functions since the
static definition of boot_count_read is anyways unused.

BUG=chrome-os-partner:55473
BRANCH=None
TEST=None

Change-Id: I47e8ed76b137c32d9ea0c4967fc616edf40798e5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15997
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367363
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:17 -07:00
Lee Leahy
fe49ccfbcc UPSTREAM: drivers/intel/fsp2_0: Display FSP calls and status
Disable the chatty FSP behavior for normal builds.  Use a Kconfig value
to enable the display of the FSP call entry points, the call parameters
and the returned status for MemoryInit, SiliconInit and FspNotify. The
debug code is placed into drivers/intel/fsp2_0/debug.c.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I18e207053ef6542912f0f0b8125e874888cb52fb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15989
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367362
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:14 -07:00
Patrick Georgi
ffda4b3d22 UPSTREAM: i2c/w83795: Fix chip type message
(val & 4) == 1 is always false. Since val & 4 is either zero or
non-zero, just drop the second test (for "== 1").
Validated against the data sheet that this is really the right register,
bit and value.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ie2a8aa09bd9c7c43608bda49c9101a87b9bdcdad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1241864
Reviewed-on: https://review.coreboot.org/16009
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/367361
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:12 -07:00
Patrick Georgi
b8f7e22390 UPSTREAM: amd/amdfam10: eliminate dead code
if (gart) { foo = gart?a:b; } never evaluates to foo=b.

BUG=None
BRANCH=None
TEST=None

Change-Id: I9d7d2e54797bce6f4e4138530af9295b15c90753
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347365
Reviewed-on: https://review.coreboot.org/16008
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/367360
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-09 17:11:10 -07:00
Kan Yan
d93520fab1 soc/qualcomm/ipq40xx: Reduce the delay in I2C.
BUG=b:28942403
TEST=Boot up and TPM functions normally.
BRANCH=None

3ms delay is sufficient for qup_i2c_write_fifo_flush().

Change-Id: I202f5b8a1ef62bb039c56ba5a25b48b205cf4a67
Signed-off-by: Kan Yan <kyan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/357961
Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org>
Reviewed-by: SARAVANAKUMAR SUDALAI <ssudalai@qti.qualcomm.com>
2016-08-08 20:19:59 -07:00
Julius Werner
c526906f99 rockchip/rk3399: Add code to neuter Type-C PHY for firmware USB
The Rockchip RK3399 integrates a USB Type-C PHY in charge of things like
SuperSpeed line muxing for rotated cable orientations in the SoC. While
fancy, this is very complicated and we don't want to implement support
for the whole thing in firmware. The USB Type-C standard has
intentionally been designed in a way that the USB 2.0 (HighSpeed) lines
always "just work" in any orientation (by just shorting different pins
in the connector together) so that simple use cases like ours can get
basic USB functionality without much hassle.

However, a semi-configured Type-C PHY can confuse USB 3.0 capable
devices into thinking we're actually supporting SuperSpeed, and fail at
that rather than establishing a reliable HighSpeed connection. This
patch sets enough bits in the Type-C PHY to electrically isolate the
SuperSpeed lines from the connector so that the connected device isn't
going to get any fancy ideas and reliably falls back to USB 2.0.

Also clean up the rest of the USB code while we're at it: avoid writing
a few bits that are already in the right state from their reset values
anyway, or reading values whose content we already know for this SoC.
Rename the USB controllers to the name actually used in the Rockchip
documentation (USB OTGx) rather than the name blindly copied from
Exynos code (USB DRDx).

BRANCH=None
BUG=chrome-os-partner:54621
TEST=Plug a USB 3.0 Patriot Memory stick into both ports in all
orientations, observe how it gets reliably detected now (safe for some
known hardware issues on my board).

Change-Id: Ie80a201a58764c4d851fe4a5098a5acfc4bcebdf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366160
Reviewed-by: liangfeng wu <wulf@rock-chips.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-by: <515506667@qq.com>
2016-08-08 20:19:49 -07:00
Kyösti Mälkki
32540462c8 UPSTREAM: console: Drop leftover struct console_driver
BUG=None
BRANCH=None
TEST=None

Change-Id: Iffef51354d09c4a399661be27179c88e054d086a
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/16007
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/366306
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-08 18:22:18 -07:00
Prabal Saha
c2a622b5c6 UPSTREAM: intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano
Without this patch, eDP output is non-functional pre-graphics driver
regardless of payload (SeaBIOS, Tianocore) or video init method
(VBIOS, GOP driver) and once the standard Windows Intel HD graphics
driver is loaded.

Test: Boot Windows on peppy and auron_paine, install Intel HD
Graphics driver, observe functional eDP output with full video
acceleration.

Debugging method: adjust location of call to run VBIOS within
coreboot, observed that eDP output functional if the VBIOS is run
before the power optimizer lines, broken if run afterwards.

BUG=None
BRANCH=None
TEST=None

Change-Id: I8c7fd6897df771713a6e4440d1256e237c436658
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/15261
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/366305
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-07 21:43:48 -07:00
Lee Leahy
f83b9dcb37 UPSTREAM: soc/intel/quark: Enable use of hard reset
Select HAVE_HARD_RESET in the KCONFIG file to enable use of the
hard_reset routine.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: Ie7abfeec60d26acb0b0af02d3abf2f3e99875e91
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15992
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366304
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-07 21:43:46 -07:00
Lee Leahy
aac0d13ecc UPSTREAM: soc/intel/common: Fix build error in reset.c
Fix build error caused by macro substitution in the function definition
when the Kconfig value HAVE_HARD_RESET is not selected.

src/soc/intel/common/reset.c:36:21: error: macro "hard_reset" passed 1 arguments, but takes just 0
 void hard_reset(void)
                     ^
src/soc/intel/common/reset.c:37:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '{' token
 {
 ^
make: *** [build/bootblock/soc/intel/common/reset.o] Error 1

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I314353fae8ea30573257e0a7007b5cb4ce39d4b8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15988
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366303
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-05 11:45:22 -07:00