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UPSTREAM: soc/intel/quark: Initialize MTRRs in bootblock

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Initialize the MTRRs for use by bootblock and romstage.
Display the MTRRs.

TEST=Build and run on Galileo Gen2.

BUG=None
BRANCH=None

Change-Id: Iaa51daf2784d5e203c3b937038bad91dcb74a48c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15861
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/367392
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Lee Leahy 2016-07-25 07:11:05 -07:00 • committed by chrome-bot
parent 6702972cdb
commit c75a096c3d
2 changed files with 38 additions and 0 deletions
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37
src/soc/intel/quark/bootblock/bootblock.c
View file

@ -18,6 +18,7 @@
#include <device/pci_def.h>
#include <program_loading.h>
#include <soc/iomap.h>
#include <soc/intel/common/util.h>
#include <soc/pci_devs.h>
#include <soc/reg_access.h>
@ -47,8 +48,38 @@ static const struct reg_script hsuart_init[] = {
REG_SCRIPT_END
};
static const struct reg_script mtrr_init[] = {
/* Use write-through caching, for FSP 2.0 the cache will be invalidated
* postchar (arch/x86/exit_car.S).
*/
/* Enable the cache */
REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)),
/* Cache the SPI flash */
REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE)
| MTRR_TYPE_WRTHROUGH)),
REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE)
| MTRR_PHYS_MASK_VALID)),
/* Cache ESRAM */
REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000
| MTRR_TYPE_WRTHROUGH)),
REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff)
| MTRR_PHYS_MASK_VALID)),
/* Enable the variable MTRRs */
REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN
| MTRR_TYPE_UNCACHEABLE),
REG_SCRIPT_END
};
void bootblock_soc_early_init(void)
{
/* Initialize the MTRRs */
reg_script_run(mtrr_init);
/* Initialize the controllers */
reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
@ -60,6 +91,12 @@ void bootblock_soc_early_init(void)
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
}
void bootblock_soc_init(void)
{
/* Display the MTRRs */
soc_display_mtrrs();
}
void platform_prog_run(struct prog *prog)
{
/* Display the program entry point */

1
src/soc/intel/quark/include/soc/reg_access.h
View file

@ -20,6 +20,7 @@
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <delay.h>
#include <fsp/util.h>
#include <reg_script.h>