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UPSTREAM: google/reef: Add pull up 20K for LPC SERIRQ

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per hw team's check and info from EDS, this pin needs to be pu 20K.
Otherwise SoC may not notice interrupt request from
EC over LPC because SERIRQ line is floating.

BUG=chrome-os-partner:55586
BRANCH=none
TEST=boot ok and Quanta factory verified the keyboard issue is gone

Change-Id: I33700d2d7e3377b4dd8244f787a383e1622f9a7d
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/15951
Tested-by: build bot (Jenkins)
Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/367368
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kane Chen 2016-07-28 19:41:15 +08:00 • committed by chrome-bot
parent 097712c8f2
commit 32ba092043
2 changed files with 2 additions and 1 deletions
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2
src/mainboard/google/reef/gpio.h
View file

@ -77,7 +77,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */
/* LPC */
PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */
PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */
PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */

1
src/soc/intel/apollolake/lpc_lib.c
View file

@ -46,6 +46,7 @@ static const struct lpc_mmio_range {
};
static const struct pad_config lpc_gpios[] = {
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),