The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect.
The result is that 800MHz FSB CPUs now properly work with 667MHz RAM.
Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas
Elyes.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17038
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648
Reviewed-on: https://chromium-review.googlesource.com/400799
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously the 945gc raminit only worked for 533MHz FSB CPUs.
This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are
taken from the vendor bios of Gigabyte ga-945gcm-s2l.
The result is that 1067MHz FSB CPUs now boot without problems.
800MHz FSB cpus still don't get past romstage.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17034
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I13a6b97d2e580512155edf66c48405a153121957
Reviewed-on: https://chromium-review.googlesource.com/400798
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This removes writes to FDI related registers since there is no FDI
link on these targets. This is likely a remainder from copying code from
later targets.
TESTED on Thinkpad x200 (gm45)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16993
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad
Reviewed-on: https://chromium-review.googlesource.com/400476
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to: "Intel 965 Express Chipset Family and Intel G35 Express
Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the
dotclock is below 225MHz and 5 when its above 225MHz.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16991
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I363039b6fd92051c4be4fdc88788f27527645944
Reviewed-on: https://chromium-review.googlesource.com/400474
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG should only occur together with
MAINBOARD_HAS_NATIVE_VGA_INIT. It seems to be used to just have to have
the option to be able to select SEABIOS_VGA_COREBOOT.
This patch makes these boards use MAINBOARD_DO_NATIVE_VGA_INIT and
MAINBOARD_HAS_NATIVE_VGA_INIT to have it select SEABIOS_VGA_COREBOOT
by default when SeaBIOS is chosen.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16981
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: If0a36af1883a3d62b16a61483733be981a85e5e2
Reviewed-on: https://chromium-review.googlesource.com/400473
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This refactoring was already carried into RK3288 with commit 6911219
(edid: Add helper function to calculate bits-per-pixel dependent values)
but it seems that the code for RK3399 was copy&pasted from it too early
to pick this up. Fix that so that future Rockchip SoCs can copy&paste
the right thing.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17050
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590
Reviewed-on: https://chromium-review.googlesource.com/400464
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a --force/-F option and enable it for cbfstool write, where it has
the effect of not testing if the fmap region contains a CBFS or if the
data to write is a CBFS image.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16998
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I02f72841a20db3d86d1b67ccf371bd40bb9a4d51
Reviewed-on: https://chromium-review.googlesource.com/398759
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reef is using APL SoC SKU's with 6W TDP max. We've done
experiments and found the energy calculation is wrong with
the current VR solution. Experiments show that SoC TDP max
(6W) can be reached when RAPL PL1 is set to 12W. Therefore,
we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:56922
BRANCH=None
TEST=webGL performance(fps) not impacted before and after S3.
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/17029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I21c278e82b82d805f6925f4d9c82187825fd0aa0
Reviewed-on: https://chromium-review.googlesource.com/400117
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
In FSP1.1 all the platform resets including global was handled
on its own without any intervention from coreboot.
In FSP2.0, any reset required will be notified to coreboot
and it is expected that coreboot will perform platform reset.
Hence, implement platform global reset hooks in coreboot. If Intel
ME is in non ERROR state then MEI message will able to perform
global reset else force global reset by writing 0x6 or 0xE to
0xCF9 port with PCH ETR3 register bit [20] set.
BUG=none
BRANCH=none
TEST=Verified platform global reset is working with MEI
message or writing to PCH ETR3.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16903
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5
Reviewed-on: https://chromium-review.googlesource.com/400115
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per ME BWG, there are two mechanism to generate a Global
Reset (resets both host and Intel ME), one is through CF9h
IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set,
PMC PCI offset ACh[20]. Another is to issue the Global Reset
MEI message. Because any attempts to cause global reset without
synchronizing the two sides might cause unwanted side effects,
such as unwritten flash data that will get destroyed if the
host were to cause a global reset without informing Intel ME
firmware, the recommended method is to send a Global Reset MEI
message when the following conditions are met:
The PCH chipset firmware just needs to complete the Intel ME
Interface #1 initialization and check the Intel ME HFSTS state
if Intel ME is not in ERROR state and is accepting MEI commands
then firmware should be able to use Global Reset MEI message to
trigger global reset.
Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9
write of 0x06 or 0x0E command with PCH ETR3 register bit [20]
to perform the global reset.
BUG=none
BRANCH=none
TEST=Verified Global Reset MEI message is able to perform platform
global issue in ME good state.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16902
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If326a137eeadaa695668b76b84c510e12c546024
Reviewed-on: https://chromium-review.googlesource.com/400114
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch programs and enables BAR for ME (bus:0/
device:0x16/function:0) device to have early ME communication.
BUG=none
BRANCH=none
TEST=Verified Global Reset MEI message can able to perform platform
global reset during romstage.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17016
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332
Reviewed-on: https://chromium-review.googlesource.com/400113
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
VBOOT_EC_SLOW_UPDATE should be selected if EC_GOOGLE_CHROMEEC is used as
building coreboot with Chrome OS support & without Chrome EC gives a
build error in coreboot.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17020
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I77eed0e1bdc1ba49381b72e21b0e18f573cadff0
Reviewed-on: https://chromium-review.googlesource.com/400112
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The clearing of the PMC registers was not being called resulting
in state persisting across reboots. This state is queried and
events are added to the eventlog like 'RTC reset' events. However,
the RTC reset event is a one time thing so it should only be logged
once. Without the clearing of the state the event was logged on
every boot.
BUG=chrome-os-partner:58496
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17027
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I60aa7102977c2b1775ab8c54d1c147737d2af5e2
Reviewed-on: https://chromium-review.googlesource.com/400111
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to "G45: Volume 3: Display Register Intel 965G Express
Chipset Family and Intel G35 Express Chipset Graphics Controller" the
VSYNC end should start at bit 16. This is also how Linux (at least 4.4)
sets this register, which can be seen with intel-gpu-tools.
TESTED on Lenovo thinkpad X60 (it does not change anything).
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17015
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a
Reviewed-on: https://chromium-review.googlesource.com/400110
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The pointers printed on unaligned memory accesses are now aligned to
those printed at the end of print_trap_information.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16983
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a
Reviewed-on: https://chromium-review.googlesource.com/400106
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On other architectures, the serial ports aren't mapped at 0x3f8.
WIP: I'm not sure how exactly the dependency should be encoded in
Kconfig.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16982
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: Ia1de545325a53607f62d08e76b2f61b25edbe6ef
Reviewed-on: https://chromium-review.googlesource.com/400105
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
spike_util.h:
- (LOG_)REGBYTES and STORE are already defined in
arch/riscv/include/bits.h.
- TOHOST_CMD, FROMHOST_* are helper macros for the deprecated
Host-Target Interface (HTIF).
qemu_util.c:
- mcall_query_memory now uses mprv_write_ulong instead of first
translating the address and then accessing it normally. Thus,
translate_address isn't used anymore.
- Several functions used the deprecated HTIF CSRs mtohost/mfromhost.
They have mostly been replaced by stub implementations.
- htif_interrupt and testPrint were unused and have been deleted.
spike_util.c:
- translate_address and testPrint were unused and have been deleted.
After this commit, spike_util.c and qemu_util.c are exactly the same and
can be moved to a common location.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16985
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: I1789bad8bbab964c3f2f0480de8d97588c68ceaf
Reviewed-on: https://chromium-review.googlesource.com/400102
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some of our RK3399 devices have panel resolutions as high as 2400x1600.
With 16bpp that barely still fit into an 8MB framebuffer, but then we
changed it to 32bpp for better image quality...
Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't
be used at all on ARM64 devices, since libpayload is perfectly capable
to dynamically allocate it with the right size based on EDID-information
on this architecture. That will require some more elaborate work to be
fixed with later patches.
BRANCH=gru
BUG=chrome-os-partner:58044
TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the
lower half of the screen that overflowed our allocated framebuffer
preserved from the last boot as soon as the backlight turns on.
Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/399966
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
CQ-DEPEND=CL:379684
BUG=chrome-os-partner:58064
TEST=verified on hana rev0
Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/379504
Commit-Ready: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
we will switch index1 when we finish ddr initialization,
and will check some status in this setp, we will reset
the system if we don't get the right status during 100ms,
we also will reset system if training error happen in index1.
BUG=chrome-os-partner:57988
BRANCH=None
TEST=reset in coreboot, and never happen it again
Change-Id: Id6e8936d90e54b733ac327f8476d744b45639232
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/399681
Reviewed-by: Julius Werner <jwerner@chromium.org>
1. override write leveing value to 0x200.
When the wrdqs slave delay is changed to 0x200, the phase between dqs
and the clock is 0 degrees. The pcb layout can make sure tDQSS timing
is smaller than 0.25tck, so this value is useful for both higher and
lower frequencies.
2. disable read leveing for LPDDR3.
Read leveing result is unreliable,the value is not in the middle of
read eye. So disable read leveing and fix the read DQSn slave delay
setting for DQn to 0x080(1/4 cycle delay of the input signal).
Check by shmoo read eye and stability test, fix to 0x80 is better.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I2a5d40c0348449b2a7c609c1db65da4ed5f1c09f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jeff Chen <cym@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/396598
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
if we want to do ddr dvfs in kernel, we need index0 and
index1 training value. We only save index0 training before,
we save index1 tarining value here.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/386596
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
there is some sdram config we do not use now, drop them.
BUG=None
BRANCH=None
TEST=None
Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/399122
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
we found sdram may fail in pctl_cfg() function, so we check the status
in this function, if exceed 100ms still in this function, we will restart
the system, we also found there are rare chance fail in ddr training, also
restart system if ddr training fail.
BUG=chrome-os-partner:57988
BRANCH=None
TEST=reset in coreboot, and never happen it again
Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/397439
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds '--includes' option to 'git config --global' command
to allow user name and email to be defined in a file included from
the global gitconfig (~/.gitconfig) file.
BUG=none
BRANCH=none
TEST=make gitconfig with ~/.gitconfig including another file which
defines user.name and email.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/16912
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I4fe61078b143c3a2e26b0be69c3ca8e6f069d8b0
Reviewed-on: https://chromium-review.googlesource.com/398624
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This enables viewing more than ~20 files in the file list on the left.
Arrows are added to indicate that more items are available off-screen.
This mimics what was done in pci_module.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14546
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e
Reviewed-on: https://chromium-review.googlesource.com/398623
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Regardless of the payload chosen a file etc/ps2-keyboard-spinup
is added to cbfs. With this fix this file is only added to cbfs when
seabios is choses as a payload.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16146
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I37cf4c998856db2d297356776752643dba46a8f8
Reviewed-on: https://chromium-review.googlesource.com/398622
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some devices have no LVDS output but if no VGA is connected or
no EDID can be found, it will try to init LVDS.
This patch detects the presence of an LVDS panel and makes sure that
LVDS is not initialized when it is absent.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16513
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7
Reviewed-on: https://chromium-review.googlesource.com/397913
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The CPU_MICROCODE_BLOB_CBFS_LOC should only be specified for COREBOOT CBFS,
not for other CBFS.
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16932
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I58bb289e6c9add2647876ef817b7920f6e7b427a
Reviewed-on: https://chromium-review.googlesource.com/397912
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reuses linux code (at least 4.1) to compute the graphic clock
divisors for LVDS displays on the gm45 northbridge.
The divisors m1, m2, n, p1, p2 need to be such that
"BASE_FREQUECY * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)
/ (p1 * p2)" is as close as possible to the target_frequency.
On g4x hardware the BASE_FREQUENCY is 96000kHz.
This potentially increases LVDS display compatibility.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I2323af5756431e89769f95059790f5a922af14b4
Reviewed-on: https://chromium-review.googlesource.com/397911
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Requesting low power acpi cpu c-states has two software interfaces:
Using P_LVLx I/O reads or using equivalent MWAIT requests.
This change makes it more consistent with newer targets that use MWAIT
requests.
There also exists extended intel acpi c-states which can be enabled
in two ways:
- using a substate hint to the mwait request (defined in bios);
- setting a model specific register (msr)
Currently this is done by setting the right msr bits but with this
change one can experiment by adding substate hints.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14801
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c
Reviewed-on: https://chromium-review.googlesource.com/397909
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
