Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: mainboard/google/reef: Configure PERST pin for reef DVT

Browse source 
Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST
during s0ix entry.

BUG=chrome-os-partner:55877
BRANCH=None

TEST=S0ix functional on DVT

Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>

Reviewed-on: https://review.coreboot.org/17030
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875
Reviewed-on: https://chromium-review.googlesource.com/400460
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vaibhav Shankar 2016-10-14 16:08:32 -07:00 • committed by chrome-bot
parent 9e76ce58d1
commit b90acd31a6
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/reef/variants/baseboard/devicetree.cb
View file

@ -15,7 +15,7 @@ chip soc/intel/apollolake
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_PRT0_UDEF"
register "prt0_gpio" = "GPIO_122"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.