It also fixes lzma compression in lar to fix the silent memory
corruption that was possible when files didn't compress well.
It adds some comments to both files and the file that calls them.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@658 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@657 f3766cd6-281f-0410-b1cd-43a5c92072e9
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
This was committed as r3044 in coreboot v2.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@654 f3766cd6-281f-0410-b1cd-43a5c92072e9
changed during run time. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@651 f3766cd6-281f-0410-b1cd-43a5c92072e9
Set manual settings for dbe62 PLL; the auto settings are giving
slightly wrong values
Add call to dumplxmsr in dbe62 initram main()
Change dumplxmsr to void parameter
Add dumplxmsrs function to geodelx raminit support code
Correct spelling of CAS.
The big one: set spd variables correctly.
The not so big one: there is a bug in com2 enable I don't understand.
For now comment out two offending lines. The cs5536 debug prints
should be reduced later.
Change fuctory to factory. It's funny but confusing.
This patch also takes into account carl-daniel and uwe's comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@649 f3766cd6-281f-0410-b1cd-43a5c92072e9
LAR archive, the LAR utility will segfault. This is reproduced easily by
zerofilling the LAR, then adding anything to it.
Looking at the code, the reason is obvious:
lar_empty_offset() can return an error code (-1). None of the callers
check for an error code, they simply assume the return value is valid.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@647 f3766cd6-281f-0410-b1cd-43a5c92072e9
Tested on real hardware, some weirdness remains, probably related to
IRQ routing.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@643 f3766cd6-281f-0410-b1cd-43a5c92072e9
removed the ELF loader from coreboot v3. This adds a Kconfig option
PAYLOAD_ELF_LOADER which builds the loader into v3. In order to make it a
little safer, I changed PAYLOAD_PREPARSE_ELF to PAYLOAD_NO_PREPARSE_ELF and
made that option depend on PAYLOAD_ELF_LOADER so that no one adds an unparsed
ELF without the loader.
One part that was strange to me was that I first tried adding elfboot.o and
archelfboot.o to the beginning of the list of object files. I added them to
the end of the list instead.
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@640 f3766cd6-281f-0410-b1cd-43a5c92072e9
path handling is built into lar, just use it.
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@639 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on dbe62. I had to run cs5536/stage1.c through indent -kr -i8 because emacs is somehow
confused by parts of it. Weird. indent made some parts ugly, at least to my eyes. Oh well.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@638 f3766cd6-281f-0410-b1cd-43a5c92072e9
This includes:
- the working power button patch.
- onchipuart2 for very early startup -- this will be replaced with a better mechanism soon.
- dts mod for powerbutton on cs5536
- dbe62 dts fix for COM1 setup
- ram check call in dbe62 initram.c
- Carl-Daniel's fix to detect incorrect access to spd variables.
- more debug prints in geodelx northbridge support code.
This is cumulative since we're lagging on acks a bit and it's hard to keep this
stuff all seperated out since it involves a common set of files. I'd like to get
it acked and in tree today if possible. It's a very small set of lines changed so please
forgive me for the cumulative nature.
Thanks
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@636 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Don't make write_phys/read_phys static, they can be useful elsewhere.
- Rename write_phys/read_phys to ram_write_phys/ram_read_phys for
consistency with the other RAM-related functions.
- Simplify some parts of the code a bit.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@635 f3766cd6-281f-0410-b1cd-43a5c92072e9
makes use of functions that were already defined. It also adds greedy name
matching for listing and extracting archives, which allows recursive descent
into the lar directory structure.
changes file-by-file:
util/lar/lar.c:
add more options to the usage message
use get_larsize() instead of using larsize
rearrange errors from parsing args to be more correct
util/lar/stream.c:
change elfname size to MAX_PATHLEN instead of 64
make file_in_list greedy with filename matches
change total_size calculation to include file names
change lar_add_entry to use header_len function instead of reinventing
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@632 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add a nasty warning if one of the cases triggers because that should
not happen. We should fix the cases where the warning triggers.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@631 f3766cd6-281f-0410-b1cd-43a5c92072e9
Factor out write_pirq_routing_table() for all GeodeLX targets.
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
tested on alix1c. Boots, USB, graphics, and ethernet all work.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@629 f3766cd6-281f-0410-b1cd-43a5c92072e9
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.
svn is unable to create a valid patch for what I did, so I'll have to
commit this myself. To reproduce, perform the following commands, then
apply the patch:
svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h
svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h
svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h
svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
tested on alix1c. Boots, USB, graphics, and ethernet all work.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@628 f3766cd6-281f-0410-b1cd-43a5c92072e9
file struct for pathname and compression, so that directories can be correctly
recursed.
file-by-file:
util/lar/lar.c:
make error messages more verbose
pass a pointer to the file structure instead of the name
parse the name here with lar_process_name
util/lar/lib.c:
change handle_directory to use a path name and respect nocompress
change add_files to use pre-processed names
use sensible defaults for new file members when listing or extracting
free pathname if allocated
util/lar/lib.h:
add new members to struct file
change prototypes of add_files and lar_add_file
util/lar/stream.c:
change lar_add_file to use pathname and compression from struct file
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@623 f3766cd6-281f-0410-b1cd-43a5c92072e9
making sure we return 0xff for nonexisiting entries and shrinking the
data structure by 85%.
As a bonus, the various initram.c for boards with fake SPD are now
almost identical.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on Alix1c, with minor mods to get it to compile. Full boot to
Linux, with graphics.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@622 f3766cd6-281f-0410-b1cd-43a5c92072e9
adding a payload. It depends on having a payload so that you can't
end up with a file with no payload and no possiblility to add one.
The default is no zero-filling.
I also added a message "ZEROING lar -z ./coreboot.rom"
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@621 f3766cd6-281f-0410-b1cd-43a5c92072e9
makes the default to parse the ELF, but leaves ELF parsing available. It
doesn't include the removal of the per-file option "nocompress".
Signed-off-by: Myles Watson <mylesgw@gmail.com>
The coreboot part looks OK and is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@620 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@619 f3766cd6-281f-0410-b1cd-43a5c92072e9
(makes it the same as create.)
Without this patch you can create a lar and recursively add a
directory to it, but you can't add one with add.
Another patch might be to make lar -l print something when you use the
directory option, but I'm not sure what was intended originally.
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@618 f3766cd6-281f-0410-b1cd-43a5c92072e9
in the pci dtc instead of the correct location in the domain.
Also fixed up some warnings on the const gliutable.
Tested on alix1c and boots to Linux, ethernet works. Still trying
to light up the display :-)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@617 f3766cd6-281f-0410-b1cd-43a5c92072e9
Note: You MUST have the later AMD VSA code that does not call bios
interrupts. If you use the older code, your boot will hang at this
point:
buf[0x20] signature is b0:10:e6:80
Call real_mode_switch_call_vsm
With post code 10
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@616 f3766cd6-281f-0410-b1cd-43a5c92072e9
file is not found instead of seg faulting.
test with:
lar -a coreboot.rom nonexistant_file.bin
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@615 f3766cd6-281f-0410-b1cd-43a5c92072e9
correct, and then populate the rest of the files. I am putting this in
now so others can help get the timing right.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@614 f3766cd6-281f-0410-b1cd-43a5c92072e9
Carl-Daniel Hailfinger wrote:
> On 18.02.2008 23:55, Marc Jones wrote:
>> Carl-Daniel Hailfinger wrote:
>>> it seems that executing VSA requires vm86 to be useful. Since we
>>> unconditionally execute the VSA, we should unconditionally require
vm86
>>> support (PCI_OPTION_ROM_RUN_VM86) via Kconfig for Geode targets. Not
>>> doing so will either cause compile failures or runtime failures.
>>>
>>> Adding
>>> select PCI_OPTION_ROM_RUN_VM86
>>> below
>>> config CPU_AMD_GEODELX
>>> did not work out for me.
>> Sorry I missed this.
>>
>> VSA requires the GDT that is in vm86.c. VSA loads similar to an
option
>> ROM so the loader does go into VM86 mode. All the other stuff like
>> interrupt support and PCI BIOS isn't needed by VSA. I think that the
>> GDT at the top of vm86.c can be moved to a header file, gdt.h or
>> something like that.
>
> northbridge/amd/geodelx/vsmsetup.c uses
> util/x86emu/vm86.c:setup_realmode_idt() but it seems most/all of the
> setup there is not needed at all for VSA. Pulling in
setup_realmode_idt
> pulls in the rest of vm86 through direct and indirect dependencies.
>
>> Care to make a patch? :)
>
I am also leaning towards removing the IDT for VSA init. There is a risk
if either an exception happens or a software interrupt is used you will
get unexpected results. What probably happens is that you jump off to
something that will eventually cause a triple fault and reboot. You may
think this is bad (and it is) but it is the same risk that coreboot runs
today. If coreboot had a generic IDT to handle exceptions, VSA init
would use the same IDT. Note that hardware INT (even timers) should
never happen as they are always masked.
I have built with no PCI_OPTION_ROM_RUN_VM86 and run this to filo.
- Show quoted text -
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones@amd.com
http://www.amd.com/embeddedprocessors
Reduce the amount of compilation errors for Geode LX targets if x86emu
or no emulation is selected instead of vm86.
Factor out GDT code from vm86.c to vm86_gdt.c
Remove IDT setup for VSA init.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-of-by: Marc Jones <marc.jones@amd.com>
This has booted to runlevel 3 and the ethernet works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@613 f3766cd6-281f-0410-b1cd-43a5c92072e9
> > Author: rminnich
> > util/x86emu/vm86.c
> > Change uses of dev_find_device to dev_find_pci_device
Unfortunately, x86emu/pcbios/pcibios.c was missed in the conversion. Fix
it to get builds with x86emu compiling again.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@612 f3766cd6-281f-0410-b1cd-43a5c92072e9
before they can be #included. That is completely counter-intuitive. Add
necessary #includes to the header files themselves.
Fix a few cases where nonexisting files were #included.
Compile tested on Qemu and Alix1C.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@611 f3766cd6-281f-0410-b1cd-43a5c92072e9
target does not yet compile due to initram breakage, but the breakage is
really old.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@609 f3766cd6-281f-0410-b1cd-43a5c92072e9
