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Make cs5536_setup_onchipuart() handle both UARTs and add missing break in dbe61 initram.

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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Tested on dbe62. I had to run cs5536/stage1.c through indent -kr -i8 because emacs is somehow 
confused by parts of it. Weird. indent made some parts ugly, at least to my eyes. Oh well. 
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@638 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-03-07 06:33:05 +00:00
parent a23b525d0a
commit f385338a15
7 changed files with 32 additions and 20 deletions
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2
mainboard/amd/norwich/stage1.c
View file

@ -42,7 +42,7 @@ void hardware_stage1(void)
* early MSR setup for the CS5536. We do this early for debug.
* Real setup should be done in chipset init via dts settings.
*/
cs5536_setup_onchipuart();
cs5536_setup_onchipuart(1);
}
void mainboard_pre_payload(void)

1
mainboard/artecgroup/dbe61/initram.c
View file

@ -102,6 +102,7 @@ u8 spd_read_byte(u16 device, u8 address)
for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
if (spd_table[i].address == address) {
ret = spd_table[i].data;
break;
}
}

2
mainboard/artecgroup/dbe61/stage1.c
View file

@ -59,7 +59,7 @@ void hardware_stage1(void)
* NOTE: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for the CS5536.
*/
cs5536_setup_onchipuart();
cs5536_setup_onchipuart(2);
}
void mainboard_pre_payload(void)

3
mainboard/artecgroup/dbe62/irq_tables.h
View file

@ -20,8 +20,7 @@
#include <pirq_routing.h>
/* Number of slots and devices in the PIR table */
#error IRQ_SLOT_COUNT does not match PIR table contents, IRQ routing setup will access uninitialied memory
#define IRQ_SLOT_COUNT 5
#define IRQ_SLOT_COUNT 3
/* Platform IRQs */
#define PIRQA 10

2
mainboard/artecgroup/dbe62/stage1.c
View file

@ -58,7 +58,7 @@ void hardware_stage1(void)
* NOTE: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for the CS5536.
*/
cs5536_setup_onchipuart2();
cs5536_setup_onchipuart(2);
}
void mainboard_pre_payload(void)

3
southbridge/amd/cs5536/cs5536.h
View file

@ -443,8 +443,7 @@
/* Function prototypes */
void cs5536_disable_internal_uart(void);
void cs5536_setup_onchipuart(void);
void cs5536_setup_onchipuart2(void);
void cs5536_setup_onchipuart(int uart);
void cs5536_stage1(void);
#endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */

39
southbridge/amd/cs5536/stage1.c
View file

@ -49,10 +49,10 @@ static void cs5536_setup_extmsr(void)
/* TODO: unsigned char -> u8? */
#if CS5536_GLINK_PORT_NUM <= 4
msr.lo = CS5536_DEV_NUM <<
(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
(unsigned char) ((CS5536_GLINK_PORT_NUM - 1) * 8);
#else
msr.hi = CS5536_DEV_NUM <<
(unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
(unsigned char) ((CS5536_GLINK_PORT_NUM - 5) * 8);
#endif
wrmsr(GLPCI_ExtMSR, msr);
@ -90,11 +90,11 @@ static void cs5536_usb_swapsif(void)
}
static const struct msrinit msr_table[] = {
{MDD_LBAR_SMB, {.hi = 0x0000f001, .lo = SMBUS_IO_BASE}},
{MDD_LBAR_GPIO, {.hi = 0x0000f001, .lo = GPIO_IO_BASE}},
{MDD_LBAR_MFGPT, {.hi = 0x0000f001, .lo = MFGPT_IO_BASE}},
{MDD_LBAR_ACPI, {.hi = 0x0000f001, .lo = ACPI_IO_BASE}},
{MDD_LBAR_PMS, {.hi = 0x0000f001, .lo = PMS_IO_BASE}},
{MDD_LBAR_SMB, {.hi = 0x0000f001,.lo = SMBUS_IO_BASE}},
{MDD_LBAR_GPIO, {.hi = 0x0000f001,.lo = GPIO_IO_BASE}},
{MDD_LBAR_MFGPT, {.hi = 0x0000f001,.lo = MFGPT_IO_BASE}},
{MDD_LBAR_ACPI, {.hi = 0x0000f001,.lo = ACPI_IO_BASE}},
{MDD_LBAR_PMS, {.hi = 0x0000f001,.lo = PMS_IO_BASE}},
};
/**
@ -147,15 +147,15 @@ void cs5536_disable_internal_uart(void)
* Disable and reset them and configure them later (SIO init).
*/
msr = rdmsr(MDD_UART1_CONF);
msr.lo = 1; /* Reset */
msr.lo = 1; /* Reset */
wrmsr(MDD_UART1_CONF, msr);
msr.lo = 0; /* Disable */
msr.lo = 0; /* Disable */
wrmsr(MDD_UART1_CONF, msr);
msr = rdmsr(MDD_UART2_CONF);
msr.lo = 1; /* Reset */
msr.lo = 1; /* Reset */
wrmsr(MDD_UART2_CONF, msr);
msr.lo = 0; /* Disable */
msr.lo = 0; /* Disable */
wrmsr(MDD_UART2_CONF, msr);
}
@ -182,7 +182,7 @@ static void cs5536_setup_cis_mode(void)
*
* See page 412 of the AMD Geode CS5536 Companion Device data book.
*/
void cs5536_setup_onchipuart(void)
void cs5536_setup_onchipuart1(void)
{
struct msr msr;
@ -238,7 +238,8 @@ void cs5536_setup_onchipuart2(void)
outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
/* Set: GPIO 3 + 3 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
outl(GPIOL_3_SET | GPIOL_4_SET,
GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
/* set address to 3F8 */
msr = rdmsr(MDD_LEG_IO);
@ -255,6 +256,18 @@ void cs5536_setup_onchipuart2(void)
wrmsr(MDD_UART2_CONF, msr);
}
void cs5536_setup_onchipuart(int uart)
{
switch (uart) {
case 1:
cs5536_setup_onchipuart1();
break;
case 2:
cs5536_setup_onchipuart2();
break;
}
}
/**
* Board setup.