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https://github.com/fail0verflow/switch-coreboot.git
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Add northbridge/amd/geodelx/raminit.c to the Artecgroup DBE61 makefile.
Completely replace DBE61 initram code by Alix.1C initram code. svn rm mainboard/artecgroup/dbe61/initram.c svn cp mainboard/pcengines/alix1c/initram.c \ mainboard/artecgroup/dbe61/initram.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@610 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger
parent
79252b2ccc
commit
975d9ef2ef
2 changed files with 94 additions and 95 deletions
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@ -22,6 +22,7 @@
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
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INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/amd/geodelx/raminit.c \
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$(src)/arch/x86/geodelx/geodelx.c
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STAGE2_MAINBOARD_OBJ =
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@ -29,120 +29,118 @@
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#include <msr.h>
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#include <io.h>
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#include <amd_geodelx.h>
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <northbridge/amd/geodelx/raminit.h>
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#include <spd.h>
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#define MANUALCONF 0 /* Do automatic strapped PLL config. */
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#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIVIL_LBAR_GPIO 0x5140000c
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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#define GPIO_BASE 0x6100 /* Mainboard-specific */
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/** Empty function to always fail SMBus reads. */
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int smbus_read_byte(unsigned device, unsigned address)
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{
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return -1;
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}
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static void init_gpio(void)
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{
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struct msr msr;
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printk(BIOS_DEBUG, "Initializing GPIO module...\n");
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/* Initialize the GPIO LBAR. */
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msr.lo = GPIO_BASE;
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msr.hi = 0x0000f001;
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wrmsr(DIVIL_LBAR_GPIO, msr);
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msr = rdmsr(DIVIL_LBAR_GPIO);
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printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n",
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msr.hi, msr.lo);
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}
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static void sdram_hardwire(void)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5)
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*/
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/* Initialize GLMC registers based on SPD values, do one DIMM for now. */
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struct msr msr;
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msr.hi = 0x10075012;
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msr.lo = 0x00000040;
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wrmsr(MC_CF07_DATA, msr); /* GX3 */
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/* Timing and mode... */
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//msr = rdmsr(0x20000019);
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/* per standard bios settings */
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/*
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msr.hi = 0x18000108;
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msr.lo =
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(6<<28) | // cas_lat
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(10<<24)| // ref2act
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(7<<20)| // act2pre
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(3<<16)| // pre2act
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(3<<12)| // act2cmd
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(2<<8)| // act2act
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(2<<6)| // dplwr
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(2<<4)| // dplrd
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(3); // dal
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* the msr value reported by quanta is very, very different.
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* we will go with that value for now.
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*
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//msr.lo = 0x286332a3;
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*/
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//wrmsr(0x20000019, msr); //GX3
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}
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/* CPU and GLIU mult/div */
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#define PLLMSRhi 0x0000039C
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/* Hold Count - how long we will sit in reset */
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#define PLLMSRlo 0x00DE0000
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static const struct wmsr {
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u32 reg;
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struct msr msr;
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} dbe61_msr[] = {
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{.reg = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
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{.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
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{.reg = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
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{.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
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/* The part is a Hynix hy5du121622ctp-d43.
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*
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* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
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* Hynix
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* DDR SDRAM (5D)
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* VDD 2.5 VDDQ 2.5 (U)
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* 512M 8K REFRESH (12)
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* x16 (16)
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* 4banks (2)
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* SSTL_2 (2)
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* 4th GEN die (C)
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* Normal Power Consumption (<blank> )
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* TSOP (T)
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* Single Die (<blank>)
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* Lead Free (P)
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* DDR400 3-3-3 (D43)
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*/
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/* SPD array */
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static const u8 spdbytes[] = {
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[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
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[SPD_BANK_DENSITY] = 0x40,
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[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
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[SPD_MEMORY_TYPE] = 7,
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[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
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[SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
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[SPD_NUM_BANKS_PER_SDRAM] = 4,
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[SPD_PRIMARY_SDRAM_WIDTH] = 8,
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[SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
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[SPD_NUM_COLUMNS] = 0xa,
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[SPD_NUM_ROWS] = 3,
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[SPD_REFRESH] = 0x3a,
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[SPD_SDRAM_CYCLE_TIME_2ND] = 60,
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[SPD_SDRAM_CYCLE_TIME_3RD] = 75,
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[SPD_tRAS] = 40,
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[SPD_tRCD] = 15,
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[SPD_tRFC] = 70,
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[SPD_tRP] = 15,
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[SPD_tRRD] = 10,
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};
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static void dbe61_msr_init(void)
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u8 spd_read_byte(u16 device, u8 address)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dbe61_msr); i++)
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wrmsr(dbe61_msr[i].reg, dbe61_msr[i].msr);
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printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
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if (device != (0x50 << 1)) {
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printk(BIOS_DEBUG, " returns 0xff\n");
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return 0xff;
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}
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printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]);
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return spdbytes[address];
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}
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/**
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* Placeholder in case we ever need it. Since this file is a
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* template for other motherboards, we want this here and we want the
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* call in the right place.
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*/
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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}
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/**
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* main for initram for the PC Engines Alix 1C. It might seem that you
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* could somehow do these functions in, e.g., the cpu code, but the
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* order of operations and what those operations are is VERY strongly
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* mainboard dependent. It's best to leave it in the mainboard code.
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*/
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int main(void)
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{
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u8 smb_devices[] = {
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DIMM0, DIMM1
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};
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printk(BIOS_DEBUG, "Hi there from stage1\n");
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post_code(POST_START_OF_MAIN);
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system_preinit();
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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cpu_reg_init(0, DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done preinit\n");
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sdram_hardwire();
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mb_gpio_init();
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printk(BIOS_DEBUG, "done gpio init\n");
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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printk(BIOS_DEBUG, "done pll reset\n");
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cpu_reg_init(0, DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done cpu reg init\n");
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sdram_set_registers();
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printk(BIOS_DEBUG, "done sdram set registers\n");
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sdram_set_spd_registers(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram set spd registers\n");
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sdram_enable(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram enable\n");
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/* Check low memory */
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/* ram_check(0, 640 * 1024); */
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init_gpio();
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/*ram_check(0x00000000, 640*1024); */
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printk(BIOS_DEBUG, "stage1 returns\n");
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return 0;
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}
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