size indicated by byte 31 of SPD.
Memory is still not working; hanging in dqs training.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard/$VENDOR/$BOARD/initram.c. It's pointless to have it in the
southbridge code as well.
Kill it in the southbridge code and use mainboard code only.
Thanks to Segher for rediscovering this bug.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@830 f3766cd6-281f-0410-b1cd-43a5c92072e9
person can fix it.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@820 f3766cd6-281f-0410-b1cd-43a5c92072e9
next step is to fix up this:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
make: exit 2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
image, and fails:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
code to use it. That makes the code more readable and also less
error-prone.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@805 f3766cd6-281f-0410-b1cd-43a5c92072e9
udelay() instead which does the same, and achieve better abstraction.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@799 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is the part of the acked patch which was to become r649 but missed
in the check in.
I'm reusing the signoff and ack.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@796 f3766cd6-281f-0410-b1cd-43a5c92072e9
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.
This pepares the way for additional optimizations during compile and
link time.
Build tested and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
issues in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@776 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@774 f3766cd6-281f-0410-b1cd-43a5c92072e9
But we can start to build it now.
Add the serengeti. Now comes the fun part: trying to get it to build.
Be aware that things have changed.
Stage1 is going to need to start up the APs, load the microcode, before we can event attempt to run initram.
So we're going to need more sophisticated code than we've had in the past.
Note also that copying cache_as_ram_auto.c and hacking it is NOT an option. We're going to have to
recreate stage 1 and initram from scratch. I expect this to improve the code anyway.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com
git-svn-id: svn://coreboot.org/repository/coreboot-v3@773 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add the 8152.
Add a config variable ACPI_TABLE
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@772 f3766cd6-281f-0410-b1cd-43a5c92072e9
I would really like to remove ops_pci from the device struct.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@771 f3766cd6-281f-0410-b1cd-43a5c92072e9
Rename files and functions as needed.
There is regularity to the naming. Stage1 stuff is called stage1_*. The rest is not.
Most .c files have a corresponding .dts. The code is simpler and smaller and has less
duplication.
Most (all) romcc artifacts removed.
I've made a lot of effort to get copyright headers done correctly, using 'svn log'.
next are the 8132, 8151, and serengeti, then comes simnow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@767 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@701 f3766cd6-281f-0410-b1cd-43a5c92072e9
patch uses byte pointer and the MMIO read and write functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@696 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Eliminate a few redundant dev_find_pci_device() calls.
- Fix a compile warning intruduced in r689.
This should be an equivalence transformation.
Build tested on norwich, db800, alix.1c, alix.2c3, dbe62, dbe61.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@692 f3766cd6-281f-0410-b1cd-43a5c92072e9
Most importantly it fixes a simple programming error which made it so most of
the sets on the USB were not doing anything. The bug is also in V2.
With this fix, the DBE62 USB ports all work!
If someone clones the fix to V2, it will also fix V2. Or, we can just convince
you to move forward to V3 :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@689 f3766cd6-281f-0410-b1cd-43a5c92072e9
USB EHCI power control registers to power enables pins 1 and 2.
Why doesn't port 4 work? Who knows. That's a problem for another day.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@688 f3766cd6-281f-0410-b1cd-43a5c92072e9
Set manual settings for dbe62 PLL; the auto settings are giving
slightly wrong values
Add call to dumplxmsr in dbe62 initram main()
Change dumplxmsr to void parameter
Add dumplxmsrs function to geodelx raminit support code
Correct spelling of CAS.
The big one: set spd variables correctly.
The not so big one: there is a bug in com2 enable I don't understand.
For now comment out two offending lines. The cs5536 debug prints
should be reduced later.
Change fuctory to factory. It's funny but confusing.
This patch also takes into account carl-daniel and uwe's comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@649 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on dbe62. I had to run cs5536/stage1.c through indent -kr -i8 because emacs is somehow
confused by parts of it. Weird. indent made some parts ugly, at least to my eyes. Oh well.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@638 f3766cd6-281f-0410-b1cd-43a5c92072e9
This includes:
- the working power button patch.
- onchipuart2 for very early startup -- this will be replaced with a better mechanism soon.
- dts mod for powerbutton on cs5536
- dbe62 dts fix for COM1 setup
- ram check call in dbe62 initram.c
- Carl-Daniel's fix to detect incorrect access to spd variables.
- more debug prints in geodelx northbridge support code.
This is cumulative since we're lagging on acks a bit and it's hard to keep this
stuff all seperated out since it involves a common set of files. I'd like to get
it acked and in tree today if possible. It's a very small set of lines changed so please
forgive me for the cumulative nature.
Thanks
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@636 f3766cd6-281f-0410-b1cd-43a5c92072e9
Factor out write_pirq_routing_table() for all GeodeLX targets.
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
tested on alix1c. Boots, USB, graphics, and ethernet all work.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@629 f3766cd6-281f-0410-b1cd-43a5c92072e9
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.
svn is unable to create a valid patch for what I did, so I'll have to
commit this myself. To reproduce, perform the following commands, then
apply the patch:
svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h
svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h
svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h
svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
tested on alix1c. Boots, USB, graphics, and ethernet all work.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@628 f3766cd6-281f-0410-b1cd-43a5c92072e9
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which
will come once this is in.
This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did
not work out, and it revealed a flaw in the design. The result?
- no more ids in the various dts files.
- the constructor struct is gone -- one less struct, nobody liked the
name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead.
- lpc replaced with ioport
All the changes below stem from this "simple" change.
I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!
TODO:
1. Change limitation in dtc that makes it hard to use hex in pci@
notation.
Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.
I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c,
so I suspect one of today's "clean up commits" broke something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
consumes one device at a time. This helps avoid array handling in the
dts and allows us to use generic disabling infrastructure.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@600 f3766cd6-281f-0410-b1cd-43a5c92072e9
those we had in v2 and before r385.
This causes pm_chipset_init() to be called on Geode LX.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Builds and run to filo.
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@595 f3766cd6-281f-0410-b1cd-43a5c92072e9
the .constructor struct member.
This error is so subtle that we might consider changing the device code; or at least
working on the documentation to make it more clear. The key question: do we ever want
an operations struct that can NOT operate as a device constructor? When this code was
designed over a year ago, it seemed that we might; now, it is not so certain.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@577 f3766cd6-281f-0410-b1cd-43a5c92072e9
Press <Enter> for default boot, or <Esc> for boot prompt...
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200
malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks)
malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks)
file_open: dev=hda1, path=/vmlinuz
ide_probe: ide_probe drive #0
ide_probe: ctrl 1188096 base 0
find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80
find_ide_controller: primary channel: compatibility mode
find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4
Sadly, it locks up at this point, but this is still progress.
I realize the location of the defines is a little odd, but I think it is useful to have
them right next to the function that uses them.
Index: southbridge/amd/cs5536/cs5536.c
cs5536.c: add ide support functions from v2
Index: mainboard/pcengines/alix1c/dts
Correct error in southbridge pcipath. Add enable_ide to dts.
Index: southbridge/amd/cs5536/dts
Add dts for enable_ide.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@575 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix spd_read_byte prototype.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@567 f3766cd6-281f-0410-b1cd-43a5c92072e9
/config/ = "northbridge/amd/geodelx";
Then the file northbridge/amd/geodelx/dts is read in and processed.
Magic(TM) appends the name "/dts" to the path.
This hack is fine with chips that only do one thing.
But some (all) northbridge parts play several roles: APIC cluster, PCI domain
device, and PCI device. The result is a need for more than one dts, since
there are three possible devices, with three types of IDs, and so on.
To keep things sane, I am proposing to enable multiple dts files in a
directory, names (e.g., nothing required here):
domaindts
pcidts
apicdts
(of course these names can be anything, this is just an example).
This change will require a change to the dtc, since we can no longer
assume just one dts file, and hence need a way to name these different
files.
The proposed change is very simple. We now require the full path name
for the file, and eliminate the Magic(TM).
So,
/config/ = "northbridge/amd/geodelx/pcidts";
will open the pcidts file.
/config/ = "northbridge/amd/geodelx/domaindts";
will open the domain dts.
Maybe we should just call it domain and pci and apic? works for me.
/config/ = "northbridge/amd/geodelx/domain";
/config/ = "northbridge/amd/geodelx/pcibridge";
/config/ = "northbridge/amd/geodelx/apic";
Changes:
dtc.c: create a new function, fopenfile, that will only open a path if it
really is a file. Modify dtc_open_file to use this function. fopenfile
assumes "-" means stdin; should it, or should I move that assumption back
to dtc_open_file?
dtc.h: add prototypes
dtc-parser.y: Given a config path, open the path.
southbridge/amd/cs5536/cs5536.c: example of how C code changes
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Please see the comments below, but they do not have to be addressed for
this commit, just keep them in mind for future commits in that area.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@566 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remove old vendor,device struct members since we are now using the
device_id struct.
Change declaration of dev_find_device to use device_id struct.
device/device_util.c
Change dev_find_device to use device_id struct instead of vendor, device
parameters.
Add convenience function, dev_find_pci_device, to make it easier for
users.
device/pci_device.c
Change uses of dev->vendor and dev->device to dev->id.
Change prints of dev->vendor, dev->device to use the
dev_id_string function.
device/pci_rom.c
Change uses of dev->vendor and dev->device to dev->id.
southbridge/amd/cs5536/cs5536.c
Change uses of dev_find_device to dev_find_pci_device
southbridge/amd/cs5536/dts
Add pciid of the cs5536
northbridge/amd/geodelx/dts
add pciid of the geodelx northbridge.
util/x86emu/vm86.c
Change uses of dev_find_device to dev_find_pci_device
With these changes, the chipsetinit function now finds the southbridge
in the static tree, which is the first time this has worked in v3.
This success in turn means that the chipsetinit code is running for the
first time.
We are still failing in "Finding PCI configuration type"
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@558 f3766cd6-281f-0410-b1cd-43a5c92072e9
post_code.c (thus drop it from console.h).
Instead, have console.h #include post_code.h and drop other
explicit #includes of post_code.h in the code; console.h is already
included in pretty much every file.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@513 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Simplify lots of code, especially msr-related code.
- Move struct msrinit declaration into msr.h as we use it quite often
and there's no use to duplicate it again and again in each file.
- Remove unrequired variable usage (e.g. numEnabled, msrnum, val, port).
- Remove useless comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@464 f3766cd6-281f-0410-b1cd-43a5c92072e9
* statically link linuxbios.initram for now (depends on printk, post_code
and die)
* greatly simplify all makefiles by creating a global Rules.make
* use $(dir $@) in Makefiles instead of absolute paths for mkdir..
* clean up Makefiles by calling components' code locally instead of in the
Makefile. (Remember: one day, no code per mainboard)
* unconditionally create .xcompile in case it changed
* add NM to xcompile
* create $(obj)/linuxbios.map with all symbols of all stages
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@463 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Use 'static' for functions and structs which are not meant to be public.
- Use 'const' for variables which are not meant to be modified.
- Move some prototypes into legacy.h where they belong.
- Drop prototypes for non-existing functions.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@460 f3766cd6-281f-0410-b1cd-43a5c92072e9
Instead of having lots of almost-empty Kconfig files all over the place,
we now collect all the "book-keeping" information (as opposed to real
LinuxBIOS configuration stuff) in one Kconfig file. The benefits are obvious.
Say we have (at some point in the future) 30 supported northbridges, 30
southbridges, and 30 Super I/O chips. That would make 90 useless Kconfig
files with just one or two lines in them, spread all over the place.
With this new approach we would instead have no additional Kconfig
files, just a list of all 90 supported chip(set)s in one Kconfig file.
For "real" config options we would still use Kconfig files in
(e.g.) southbridge/foo/bar/Kconfig, of course, which are manually "hooked"
into the config system in the top-level Kconfig file.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@441 f3766cd6-281f-0410-b1cd-43a5c92072e9
