mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
With this set of changes FILO now reliably finds the IDE controller.
Press <Enter> for default boot, or <Esc> for boot prompt... boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks) malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks) file_open: dev=hda1, path=/vmlinuz ide_probe: ide_probe drive #0 ide_probe: ctrl 1188096 base 0 find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80 find_ide_controller: primary channel: compatibility mode find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4 Sadly, it locks up at this point, but this is still progress. I realize the location of the defines is a little odd, but I think it is useful to have them right next to the function that uses them. Index: southbridge/amd/cs5536/cs5536.c cs5536.c: add ide support functions from v2 Index: mainboard/pcengines/alix1c/dts Correct error in southbridge pcipath. Add enable_ide to dts. Index: southbridge/amd/cs5536/dts Add dts for enable_ide. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@575 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
parent
68b88818b1
commit
010f751a48
3 changed files with 37 additions and 7 deletions
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@ -40,8 +40,9 @@
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};
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southbridge {
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/config/("southbridge/amd/cs5536/dts");
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pcipath = "0xf,1";
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pcipath = "0xf,0";
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enabled;
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enable_ide = "1";
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};
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superio {
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/config/("superio/winbond/w83627hf/dts");
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@ -541,6 +541,35 @@ void chipsetinit(void)
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}
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}
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#define IDE_CFG 0x40
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#define CHANEN (1L << 1)
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#define PWB (1L << 14)
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#define CABLE (1L << 16)
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#define IDE_DTC 0x48
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#define IDE_CAST 0x4C
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#define IDE_ETC 0x50
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/**
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* Enabled the IDE. This is code that is optionally run if the ide_enable is set
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* in the mainboard dts.
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*
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* @param dev The device
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*/
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static void ide_init(struct device *dev)
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{
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u32 ide_cfg;
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printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__);
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/* GPIO and IRQ setup are handled in the main chipset code. */
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// Enable the channel and Post Write Buffer
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// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
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ide_cfg = pci_read_config32(dev, IDE_CFG);
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ide_cfg |= CHANEN | PWB;
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pci_write_config8(dev, IDE_CFG, ide_cfg);
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}
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/**
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* TODO.
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*
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@ -576,6 +605,9 @@ static void southbridge_init(struct device *dev)
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enable_USB_port4(sb);
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if (sb->enable_ide)
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ide_init(dev);
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#warning Add back in unwanted VPCI support
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#if 0
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/* Disable unwanted virtual PCI devices. */
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@ -588,12 +620,6 @@ static void southbridge_init(struct device *dev)
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#endif
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}
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static void southbridge_enable(struct device *dev)
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{
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printk(BIOS_ERR, "cs5536: Enter %s: dev is %p\n", __FUNCTION__, dev);
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printk(BIOS_ERR, "cs5536: Exit %s: dev is %p\n", __FUNCTION__, dev);
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}
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/**
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* A slightly different enable resources than the standard.
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* We grab control here as VSA has played in this chip as well.
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@ -37,6 +37,9 @@
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/* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */
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enable_ide_nand_flash = "0";
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/* IDE: enable CS5536 IDE. There may be a different IDE controller on board */
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enable_ide = "0";
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/* Enable USB Port 4 (0:host 1:device). */
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enable_USBP4_device = "0";
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