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With this set of changes FILO now reliably finds the IDE controller.

Browse source 
Press <Enter> for default boot, or <Esc> for boot prompt...  
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200
malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks)
malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks)
file_open: dev=hda1, path=/vmlinuz
ide_probe: ide_probe drive #0
ide_probe: ctrl 1188096 base 0
find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80
find_ide_controller: primary channel: compatibility mode
find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4

Sadly, it locks up at this point, but this is still progress.

I realize the location of the defines is a little odd, but I think it is useful to have 
them right next to the function that uses them. 

Index: southbridge/amd/cs5536/cs5536.c
cs5536.c: add ide support functions from v2
Index: mainboard/pcengines/alix1c/dts
Correct error in southbridge pcipath. Add enable_ide to dts. 
Index: southbridge/amd/cs5536/dts
Add dts for enable_ide.


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@575 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-02-07 06:33:49 +00:00
parent 68b88818b1
commit 010f751a48
3 changed files with 37 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
mainboard/pcengines/alix1c/dts
View file

@ -40,8 +40,9 @@
};
southbridge {
/config/("southbridge/amd/cs5536/dts");
pcipath = "0xf,1";
pcipath = "0xf,0";
enabled;
enable_ide = "1";
};
superio {
/config/("superio/winbond/w83627hf/dts");

38
southbridge/amd/cs5536/cs5536.c
View file

@ -541,6 +541,35 @@ void chipsetinit(void)
}
}
#define IDE_CFG 0x40
#define CHANEN (1L << 1)
#define PWB (1L << 14)
#define CABLE (1L << 16)
#define IDE_DTC 0x48
#define IDE_CAST 0x4C
#define IDE_ETC 0x50
/**
* Enabled the IDE. This is code that is optionally run if the ide_enable is set
* in the mainboard dts.
*
* @param dev The device
*/
static void ide_init(struct device *dev)
{
u32 ide_cfg;
printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__);
/* GPIO and IRQ setup are handled in the main chipset code. */
// Enable the channel and Post Write Buffer
// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
ide_cfg = pci_read_config32(dev, IDE_CFG);
ide_cfg |= CHANEN | PWB;
pci_write_config8(dev, IDE_CFG, ide_cfg);
}
/**
* TODO.
*
@ -576,6 +605,9 @@ static void southbridge_init(struct device *dev)
enable_USB_port4(sb);
if (sb->enable_ide)
ide_init(dev);
#warning Add back in unwanted VPCI support
#if 0
/* Disable unwanted virtual PCI devices. */
@ -588,12 +620,6 @@ static void southbridge_init(struct device *dev)
#endif
}
static void southbridge_enable(struct device *dev)
{
printk(BIOS_ERR, "cs5536: Enter %s: dev is %p\n", __FUNCTION__, dev);
printk(BIOS_ERR, "cs5536: Exit %s: dev is %p\n", __FUNCTION__, dev);
}
/**
* A slightly different enable resources than the standard.
* We grab control here as VSA has played in this chip as well.

3
southbridge/amd/cs5536/dts
View file

@ -37,6 +37,9 @@
/* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */
enable_ide_nand_flash = "0";
/* IDE: enable CS5536 IDE. There may be a different IDE controller on board */
enable_ide = "0";
/* Enable USB Port 4 (0:host 1:device). */
enable_USBP4_device = "0";