Fix the following errors and warnings detected by checkpatch:
ERROR: open brace '{' following struct go on the same line
ERROR: return is not a function, parentheses are not required
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement
TEST=None
Change-Id: Ieba9181e756b7c3600cf88e56d04f69abfc33569
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8a9c7dc087
Original-Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18884
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/457359
Fix the following issue detected by checkpatch:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=None
Change-Id: I4936fc41e8b7b9a11398445b95dd2591acad5f37
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23602dfd68
Original-Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18873
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/457358
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '<=' (ctx:VxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: spaces required around that '>=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: space required before the open parenthesis '('
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no space before tabs
WARNING: please, no spaces at the start of a line
False positives are generated for the following test:
WARNING: space prohibited between function name and open parenthesis '('
in both pei_data.h and pei_wrapper.h
TEST=None
Change-Id: I751eb76f0e665a99e56ed2b051215d367238e12b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 26b7cd0fa8
Original-Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18872
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457357
With a recent patch (google/veyron_*: Add new Micron and Hynix modules)
we switched RAM codes for Veyron boards to tri-state since we were
running out of binary numbers. Unfortunately we only tested that change
on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and
Mighty. The "high" RAM code pins on those boards were incorrectly
strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and
Speedy), which is too high to overpower the SoC-internal pull-down we
use to differentiate "high" from "tri-state". Since we already used
tri-state codes on some Minnie and Speedy SKUs we have to hack up the
code to work differently on these two groups of boards to keep
everything working.
BRANCH=veyron
BUG=b:36279493
TEST=Compiled, confirmed ram_code called the right function depending on
board.
Change-Id: I5ff76b5774952ed9821d47f82ed477fa4e570612
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2d99f3b158
Original-Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18859
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/457059
Now that EC on poppy is stable, it is time to switch on EC SW sync.
BUG=b:36178824
BRANCH=None
TEST=Verified that EC SW sync is done properly and device boots to OS.
Change-Id: I80b48146bbc6aaf967047f8dd80a3e1991eca66c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 336a34c81b
Original-Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18838
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457058
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Apollo Lake system such as Snappy.
The cause is the Linux Kernel setting the firmware reset time to
100 ms by default.
This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.
BUG=b:35774937
BRANCH=none
TEST=update snappy coreboot and test i/o latency is under 100ms
Change-Id: I3fd354bb3ad4fbe6c5a0033c6a5406c61a984300
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07f60aa56f
Original-Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com>
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a
Original-Reviewed-on: https://review.coreboot.org/18806
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/457057
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: Ied84c3bca185de9d10102e4aeb3e905fc58ed43b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f80ccc357
Original-Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18864
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457056
Fix the following warnings detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: plain inline is preferred over __inline__
TEST=Build and run on Galileo Gen2
Change-Id: I7404123285a4b009b215b9efa101cebfd8d8a6ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e5f29e8bf8
Original-Change-Id: I8ba98dfe04481a7ccf4f3b910660178b7e22a4a7
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18863
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456315
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: space prohibited after that open square bracket '['
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space required after that ';' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:ExV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: spaces required around that ':' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '||' (ctx:VxW)
ERROR: space prohibited before that '++' (ctx:WxO)
ERROR: need consistent spacing around '+' (ctx:WxV)
ERROR: spaces required around that '<' (ctx:WxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: "(foo*)" should be "(foo *)"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "foo * bar" should be "foo *bar"
ERROR: code indent should use tabs where possible
WARNING: space prohibited between function name and open parenthesis '('
WARNING: unnecessary whitespace before a quoted newline
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
WARNING: Unnecessary space before function pointer arguments
TEST=Build and run on Galileo Gen2
Change-Id: I79bd758d05c64541b0b4e3c50148d28e98642d09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 024b13d07c
Original-Change-Id: I2d7e1a329c6b2e8ca9633a97b595566544d7fd33
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18862
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456314
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: open brace '{' following function declarations go on the next line
ERROR: that open brace { should be on the previous line
ERROR: else should follow close brace '}'
WARNING: braces {} are not necessary for any arm of this statement
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: I22a46be57513a7f8ca5c504c35c1c335a5ae2c03
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c7c6f7213
Original-Change-Id: I13d1967757e106c8300a15baed25d920c52a1a95
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18861
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456313
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: that open brace { should be on the previous line
ERROR: return is not a function, parentheses are not required
WARNING: braces {} are not necessary for any arm of this statement
WARNING: line over 80 characters
WARNING: braces {} are not necessary for single statement blocks
WARNING: Avoid unnecessary line continuations
WARNING: break is not useful after a goto or return
WARNING: else is not generally useful after a break or return
False positives are generated by checkpatch for the following test:
ERROR: Macros with complex values should be enclosed in parentheses
TEST=Build for cyan
Change-Id: Iee0e4fbac83ded441f6123ceb7ae7f1011bc483a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d94cff6ab2
Original-Change-Id: I19048895145b138a63100b29f829ff446ff71b58
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18871
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/456312
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build for cyan
Change-Id: I3b46d8e0f3ebeae55c71c54d01475b294652505a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1072e7dcc3
Original-Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18870
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/456311
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxE)
ERROR: spaces required around that '=' (ctx:WxV)
ERROR: code indent should use tabs where possible
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no spaces at the start of a line
TEST=Build for cyan
Change-Id: I4a238c8e47032cd7c7339a26fad4b3760aa150bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6598b91fe3
Original-Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18869
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/456310
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
ERROR: Macros with complex values should be enclosed in parentheses
ERROR: "foo * bar" should be "foo *bar"
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '=' (ctx:VxW)
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration
WARNING: char * array declaration might be better as static const
WARNING: please, no space before tabs
WARNING: braces {} are not necessary for single statement blocks
WARNING: else is not generally useful after a break or return
WARNING: static const char * array should probably be static const char * const
TEST=Build for glados
Change-Id: I6662edd74e923a212392dab88dbda1d2e0b76e09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4c4ab9826
Original-Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18868
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456309
Fix the following warning detected by checkpatch:
WARNING: line over 80 characters
TEST=Build for glados
Change-Id: Ic775c43d42f363936859606b524d00c830e82984
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b439a92939
Original-Change-Id: I79341f46ca06ac052f987975ccaf975470d27806
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18867
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/456308
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build for glados
Change-Id: Ie9d2b2f4b28d9fcbc52ae68b3cffaf0401766c67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573564cca8
Original-Change-Id: Idc2ad265e8ed8cd7fd6d228cfbe4cbbcb9d3ebfc
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18866
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456307
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.
Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller. This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.
This is a clone of Duncan's patch for eve
at I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
BUG=none
BRANCH=none
TEST=test on poppy that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.
Change-Id: I7df3aea83282ea453f24e9d3e61c2a68d5f40152
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a1503e9db
Original-Change-Id: I4aaa4164cb277a98ab5d5f033632f5e16bfb779e
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18853
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456306
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.
Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller. This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.
BUG=b:35585307
BRANCH=none
TEST=test on Eve that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.
Change-Id: Idba470851244dcdabb6919b12c513b2597c81c16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 887e7936f8
Original-Change-Id: I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18836
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456305
Add support for using GPIO IRQ instead of PIRQ with an I2C device.
This allows a device to use an edge triggered interrupt that will
trigger on both high and low transitions.
The _DSD method for describing these GPIOs has a field for 'active
low' which is supposed to be 1 if the pin is active low, otherwise
is zero. The value in here doesn't mean too much for GpioInt() as
those will end up using the value from GpioInt() when it actually
requests the interrupt.
BUG=b:35581264
BRANCH=none
TEST=test on Eve board that codec IRQ can be delcared as GPIO IRQ
Change-Id: Ic8366500fb869f2d0390aa08d94bdb58ed0133d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b94e93531f
Original-Change-Id: I02c64c7fc28dc2d608ad40db889c7242892f16db
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18835
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456304
GPIO edge interrupts can report that they are ActiveBoth and will
generate an interrupt event on both rising and falling edges.
Add a macro so this type of GPIO interrupt can be used.
BUG=b:35581264
BRANCH=none
TEST=successfully use this interrupt type on Eve
Change-Id: I8787e410da3e142c7c66cc7ef2de9b62fe50cc6a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 346cfe363e
Original-Change-Id: I91408386538e442bddcacc9840e0aa14370a446c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18834
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456303
Switch some IRQ_* macros to ACPI_IRQ_* instead so they do not
fail at compile time if they are used.
BUG=b:35581264
BRANCH=none
TEST=successfully compile with ACPI_GPIO_IRQ_LEVEL_HIGH
Change-Id: I372c4844904081fa76d0cbc9ea34e156f6401ba7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9462e14065
Original-Change-Id: Id4040eca4c7c9d8f7b4f0add411d5d6fe5ed1eb8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18833
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/456302
When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.
For some builds, new toolchain and GCC-6.3 could emit
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8cf0cd97d9191e23f1f9ce0b8ae647f523a076cd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf3091bae6
Original-Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18691
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/456301
On the ASRock E350M1, with Linux 4.10 after resuming from S3, the PS/2
keyboard does not work. Adding the ASL code, fixes this.
The Linux messages change like below.
Before (equivalent to `i8042.nopnp`):
```
kernel: i8042: PNP: No PS/2 controller found.
kernel: i8042: Probing ports directly.
kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
kernel: serio: i8042 AUX port at 0x60,0x64 irq 12
kernel: mousedev: PS/2 mouse device common for all mice
```
After:
```
kernel: i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
kernel: i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
kernel: mousedev: PS/2 mouse device common for all mice
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I9bf9edfb971d3723e4ebc8b379ad0d39220d0cf0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 824416078e
Original-Change-Id: I0a06311860398cac9cf1a077e3aba75da779f45d
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18574
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/456300
Fix the following error and warnings detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
WARNING: Consecutive strings are generally better as a single string
WARNING: static const char * array should probably be static const char * const
TEST=Build and run on Galileo Gen2
Change-Id: I5834753bf10fd542d699a52cd5fe7a8bb56b4b5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4dddda294f
Original-Change-Id: I03d5d0d2db0d5e9b33c8ec807b236fe229bcc8f3
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18851
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456248
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: Iafab3ac126690df28f1fb3fff891219e8c156882
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cdc50480c4
Original-Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18850
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456247
Fix the following error and warning detected by checkpatch.pl:
ERROR: that open brace { should be on the previous line
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: I19682d7da511d778cb2c9c41b9d2cb60e560e555
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 26eeb0f8ad
Original-Change-Id: Icdd6bd9ae578589b4d42002d200fa8f83920265e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18849
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456246
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build and run on Galileo Gen2
Change-Id: I48858d8d7a2ace1f719ba46b5cb5f7751a9a8518
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 73a2894203
Original-Change-Id: I207713a3370e5a9abed4535187aa2aaeef502d6f
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18848
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456245
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_DVT_v0.6_20170314.xlsx)
1. Increase PL2 Max to 15W.
BUG=b:35583586
BRANCH=reef
TEST=build and verify PL2 Max value on electro dut
Change-Id: I73d859ce18027e954ed8fad5ef5c359d0c0cef73
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4239ff37b7
Original-Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18807
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456244
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: need consistent spacing around '-' (ctx:WxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: need consistent spacing around '<<' (ctx:VxW)
ERROR: spaces required around that '||' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration
TEST=Build and run on Galileo Gen2
Change-Id: I8307c37acfeccbd48274beaa772533ec31b718cd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9d62e7e75e
Original-Change-Id: I6602fbc8602171ab6c2f3b6c204558ad2c811179
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18847
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456243
Fix the following error and warning detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: Icb5c8dc05bb977313235c46d6eb09a821b9450c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7b5f12b9b2
Original-Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18846
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456242
Fix the following error and warnings detected by checkpatch.pl:
ERROR: trailing statements should be on next line
WARNING: storage class should be at the beginning of the declaration
WARNING: type 'long unsigned int' should be specified in [[un]signed] [short|int|long|long long] order
TEST=Build and run on Galileo Gen2
Change-Id: Ia707c6e3a6b65f12d3b1e60510b4a99bc24ea83d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dfc8a560d7
Original-Change-Id: I9cfe42cf1836cfd40ffcf67237c818543f508feb
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18845
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456241
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I7805a5121d572e07ebb155eca1f7d75efaf13f94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c5917079eb
Original-Change-Id: I56ea28826963403dc0719f40c13782c56dc97feb
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18844
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456240
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build and run on Galileo Gen2
Change-Id: I068dd20c4cbfdfb8b7a0703c3711582eaa884743
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ca9a21a43
Original-Change-Id: I97bbe8ba19680bdb99fa38daa5e18b440c338576
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18843
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456239
Fix the following warnings detected by checkpatch.pl
WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement
WARNING: else is not generally useful after a break or return
TEST=Build and run on Galileo Gen2
Change-Id: Icab33fe1dc3080d5c98cbcec1993364a06e51c5b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a15d8af140
Original-Change-Id: I2d6b22c66d52f5f2d24b15270ad4b52894adebc2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18842
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456238
Fix the following error and warning detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
TEST=Build and run on Galileo Gen2
Change-Id: Iac22e8fea19724d9ca43a96b67902b4e19018c0f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a07d0ddc44
Original-Change-Id: Ie6e4dd4c3eb0d2c44ecd008740dfc348d496fe78
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18841
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456237
Fix the following errors and warning detected by checkpatch.pl:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: need consistent spacing around '|' (ctx:WxV)
ERROR: need consistent spacing around '|' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '==' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:ExV)
WARNING: space prohibited between function name and open parenthesis '('
TEST=Build and run on Galileo Gen2
Change-Id: Ibff31d4011e7457c198b102afea9a7e8aed6aa11
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8bad6d2f90
Original-Change-Id: I61d08055b207c607d5b7d72b0094ad8e24fbd106
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18840
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/456236
Fix the following error detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
TEST=Build and run on Galileo Gen2
Change-Id: I800b829d82546f5f4f34c3ffc64ae2ece0b22811
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f94541329
Original-Change-Id: I8b5342df3f42dbb4576aecf5b0a59f195ae8511e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18839
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/455855
Add the necessary files and changes to support vboot.
TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield
1. Obtain and install a SparkFun CryptoShield.
https://www.sparkfun.com/products/13183
2. Edit src/mainboard/intel/galileo/Kconfig to select
VBOOT_WITH_CRYPTO_SHIELD
3. Use make menuconfig to update the config values and select a
payload that will fit. I used SeaBIOS which does not boot.
4. Build coreboot
5. Use the command file below to generate the signed coreboot image.
6. Flash build/coreboot.rom onto the Galileo board
7. The test is successful if verstage detects that it needs recovery
after Phase 1. This is expected because the image does not contain
the GBB section.
8. Flash build/coreboot.signed.bin onto the Galileo board
9. The test is successful if verstage reaches Phase 4 and selects SLOT
A to load the rest of the files.
commands:
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
if=build/coreboot.rom of=build/coreboot.signed.rom
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
of=build/coreboot.signed.rom
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \
count=368 if=build/coreboot.rom of=build/coreboot.signed.rom
gbb_utility \
--set --hwid='Galileo' \
-r $PWD/keys/recovery_key.vbpubk \
-k $PWD/keys/root_key.vbpubk \
build/coreboot.signed.rom
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
build/coreboot.signed.rom \
$PWD/keys \
build/coreboot.signed.rom
Change-Id: I2c19368819bc4e5794a4bb6b9dbd4f0790da6e48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 28c3f23b46
Original-Change-Id: I02eb0ef647cd34c13a5fe8be0bdbe1bb38524d0c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18821
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455854
The I2C interface for the Atmel AT97SC3204 TPM varies greatly from the
existing I2C TPM support. The Atmel part just passes the commands and
responses from the TIS layer across the I2C interface.
TEST=Build and run on Galileo Gen2 with Crypto Shield and vboot enabled
Change-Id: Ia98801459d48f33d8ec1c3f616b533e4589aafd1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b39f176a9
Original-Change-Id: Ib2ef0ffdfc12b2fc11fe4c55b6414924d4b676dd
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18800
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455853
Add debugging support for the TIS transactions for the I2C TPM chips.
TEST=Build and run on reef
Change-Id: I908d0e64230f861230bd3bfe3d3c0459b894a6c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0668e4e1f
Original-Change-Id: Ibc7e26fca781316d625f4da080f34749f18e4f9b
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18799
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/455852
Fix the following warnings detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: braces {} are not necessary for single statement blocks
WARNING: Unnecessary parentheses - maybe == should be = ?
WARNING: line over 80 characters
WARNING: missing space after return type
TEST=Build and run on Galileo Gen2
Change-Id: I2e1797473a821b9fc9a20c6c433c50945bf60eae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52ab30b13b
Original-Change-Id: I56f915f6c1975cce123fd38043bad2638717d88c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18832
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455851
Keep the BOOT0 pin triggering the MCU bootloader as an input,
so the Servo debug board doesn't have to fight with the PCH to program
it, the net already has an external pull-down to ensure that the MCU is
in normal mode at boot.
By default, do not drive the FP sensor reset from the PCH, the MCU is
now managing the reset line (but the PCH still has a connection on the
current boards).
BRANCH=none
BUG=b:36025702
TEST=manual testing, program the MCU through a Servo v2 board, and use
the FP sensor through the MCU and verify it is not stuck under reset.
Change-Id: I9bb2dfe49e0396a406fb807438ae7a8f125bb7a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08824ec8d4
Original-Change-Id: I19113b5d78013d0ab6ec5a72c6f71dd4c67a88e8
Original-Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18830
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/455850
Set the AC and DC loadline values based on the KBL-Y 2+2 defaults
that are applied by FSP. These will be tuned later and are exposed
as defaults so the engineers know what to start with.
BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values
Change-Id: I2a78f75dea7f4fce2fb8d9c4adf0090782c0171f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57e9e3be5f
Original-Change-Id: Ieae4f2b201d8210e75bdb9438070a3a2e1fda6b7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18820
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/455849
Add options to set the AC and DC loadline values for each supported
VR type so these can be tuned on a per-board basis in devicetree.cb.
BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values
Change-Id: I0c34f14c4354e567dd750873ac1c50e6ecfc5fe9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86db469871
Original-Change-Id: I2a5533d2c9fd86351c86584e3738e80ac4c1f915
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18819
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/455848
With the move to FSP 2.0 the number of VR types supported was
reduced to 4, and the VR_RING type is no longer present.
This means all existing boards using FSP 2.0 are incorrectly
passing VR configuration into FSP as the values corresponding to
"GT Sliced" and "GT Unsliced" have changed.
Fix this by updating the skylake SOC VR handling to account for
changes in the FSP configuration and no longer provide VR_RING
type when using FSP 2.0.
BUG=b:36228330
BRANCH=none
TEST=manual: build and boot on Eve
Change-Id: I7282b870cc4e6a6192f95239b8e5abc0cd63e7af
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fa8a6f4fe
Original-Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18818
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/455847
On this platform the DMICs are connected to the rt5514 DSP instead
of directly connected to the SOC. Use the new rt5514 NHLT blob
instead of the 4ch DMIC blob and add the required I2C and SPI
entries in devicetree so this can get probed properly.
BUG=b:35585307
BRANCH=none
TEST=build and boot on Eve P1 and check for rt5514 driver enumerated
by the kernel
Change-Id: I0ad047f30298f17df807715ac97d8311c0a74985
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2661a9f517
Original-Change-Id: I0f2cb532771ee1857df7f33c52a96acf96dc1f54
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18817
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/455846
Add support for describing the NHLT blob for the rt5514 DSP.
Currently this only supports 4 channel capture.
BUG=b:35585307
BRANCH=none
TEST=build and boot on Eve P1
Change-Id: I428bcfc49875e46de307fb204fe9e5300d3bff5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a75a66d67
Original-Change-Id: Ib59b56222f9aa65370fdcf9ddf25145c571b1b2e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18816
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/455845
Add the missing macro for ACPI_IRQ_LEVEL_HIGH so it can get
used by devicetree when necessary.
BUG=b:35585307
BRANCH=none
TEST=Add rt5514 SPI device with active high level IRQ on Eve board
and check that it is enumerated in the kernel
Change-Id: If1600c8d14e3a920e9f4eb1ec1e3dd62a75349c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7273e18399
Original-Change-Id: I25c7b035a198efb218f0f6b4ba3f4a1bf532bcea
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18815
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/455844
This patch make some general adaptations in relation to commit 6a489237
(mainboard/intel/leafhill: Clean up).
- add necessary defaults to Kconfig
- remove irrelevant entries from FMD file
- include romstage file for better understanding
BUG=none
BRANCH=none
TEST=none
Change-Id: I83bed6c31afb22f045f674fd8d523039bcddc9f5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0853055ef7
Original-Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18808
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/455842
