Only guard the parts that are problematic for romstage.
Also intention is to move AMD_S3LATE_RESTORE to ramstage in followup
work, it will need OemS3LateRestore.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idc337f6edd1d4647037fac177b8d0e85610e6596
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d5321c9c4
Original-Change-Id: Ie9c1fb3f3f0ab1951771ed829d4acdd8a59d8fbf
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19025
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466060
Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so the buffer is not invalidated without writeback.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib17675c8cddb8b1266f389b6a2c505713897da64
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a6e00fd36
Original-Change-Id: I3a5d497d0e25ec291f722e9f089bc8928238c3f9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19024
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466059
Logging makes it easier to track order of events as these
call-sites are scattered on various files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5392a0b83fb08c1f8797b3a8ea459fdb0d60bb7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1498efe2d0
Original-Change-Id: I428547051fd8bf487e91415dc72ee03dba13029e
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18718
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466058
The tis.c module is needlessly copying data to/from a 1260 byte
buffer on the stack. Each device's transport implementation (cr50.c
or tpm.c) maintains its own buffer, if needed, for framing purposes.
Therefore, remove the duplicated buffer.
BUG=b:36598499
Change-Id: I091309f0fd45943b974d5244ae79c01eed618f16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92190198b0
Original-Change-Id: I478fb57cb65509b5d74bdd871f1a231f8080bc2f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19061
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/466056
The spi tis_sendrecv() implementation was always returning success
for all transactions. Correct this by returning -1 on error when
tpm2_process_command() returns 0 since that's its current failure
return code.
BUG=b:36598499
Change-Id: I614d05e76f8f09e071405b1acdc68db6ab989976
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ef52cd751
Original-Change-Id: I8bfb5a09198ae4c293330e770271773a185d5061
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19058
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/466053
The tpm_info object is a global, but its symbol does not need to
be exposed to the world as its only used within tpm.c.
BUG=b:36598499
Change-Id: I10d2d75641ed3ce9d3fda27c382348c9c90542aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 445c13fb5d
Original-Change-Id: Idded3dad8d0d1c3535bddfb359009210d3439703
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19057
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/466052
In the case of start_transaction() failing the chip select is never
deasserted. Correct that by deasserting the chip select when
start_transaction() fails.
BUG=b:36598499
Change-Id: I91866a30fca8c9efae15a900722eb0fc3bebbfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5cf1fadeca
Original-Change-Id: I2c5200085eb357259edab39c1a0fa7b1d81ba7b2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19056
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/466051
Currently only 256 bytes can be written at a time using the
acpigen_write_return_byte_buffer or acpigen_write_byte_buffer API's
and there can be cases where the buffer size can exceed this, hence
increase the number of bytes that can be written.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1e7db59aca3bde85eb1f171a7e95854c1f438bcb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aca4c94057
Original-Change-Id: Ifaf508ae1d5c0eb2629ca112224bfeae1c644e58
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18966
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/466049
With COREBOOT_BUILD_DIR set, nvramcui & coreinfo were getting built
in the wrong location, causing those builds to fail.
Also, because they were built in the wrong location, the build failures
were not detected by jenkins which was looking for the junit.xml files
under the payloads directory.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iccb30a12aeebb1839ab265935b3332d6ed2f5fc1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee762fa42b
Original-Change-Id: I9d81ebabebe5d8b5f79ae63f8a5f388430e06754
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19069
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/466048
There's a missing closing brace in fillbits function of jpeg.c which
caused an avalanche of compilation errors.
This was introduced in commit
491c5b60 (src/lib: Move assignment out of if condition)
which was reviewed in gerrit at https://review.coreboot.org/18761 and it
prevents coreboot from building when CONFIG_BOOTSPLASH is set.
BUG=none
BRANCH=none
TEST=none
Change-Id: I60eb0319dd3ae170694ba8e0b570876f646d917c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d24dbf9902
Original-Change-Id: Ie10b774875fc25ce2ff613c542c15870e780a761
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19032
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/462963
Wake On Voice stream capture configuration is mono. It is sufficient
to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1.
Power saving should be visible in the boards which has more
than one DMIC connected.
BUG=None
BRANCH=None
TEST=WoV and quad channel DMIC capture works
Change-Id: Ide41768001b535141948d6d0290725ae29a744ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e2370075d
Original-Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03
Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19018
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/462959
Use the new parameters in amdfwtool to include the additional SMU
firmware into amdfw.rom.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ief97b0f10459dbdfb623f36fc5840f8662347c6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0cd2cb6cae
Original-Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19002
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462957
Change the current implementation so that multiple PSP directory
structures are not included, saving 448 KB.
AMD created a mechanism so that multiple generations of APUs, in
identical packages, may be supportable in one BIOS image. The PSP
identifies the correct directory table by checking one of two
pointers in the Embedded Firmware structure. Coreboot doesn't
implement this capability, however it has been constructing
amdfw.rom with two identical directory tables and two copies of
each PSP blob.
Tested on Bettong (Merlin Falcon / Carrizo) and Jadeite (Stoney).
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 11dfc3f621344db66d92b61d72927128ea48685f)
BUG=none
BRANCH=none
TEST=none
Change-Id: I05e17055775d02fdd61a5dfd06e6d08742219281
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7fd0bc84ff
Original-Change-Id: I139f3bfdb319af803fef64e7bd848e95945f41aa
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18990
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462956
For systems using Chrome OS, place the amdfw outside of cbfs control.
The firmware must go to a fixed position at an offset of 0x20000 into
the flash device.
Potentially improve by adding a warning or error message for the
condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash).
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1)
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f98ea97aaf8fc3a08ebc907ea0cb7a3cbc73aa3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c6be0d854a
Original-Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18435
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462955
The Stoney Ridge program has OPNs that are considered fanless. These
APUs are strapped to search for unique SMU firmware, indicated by
Type[8]=1 in the directory table entry.
Add new options to amdfwtool and include the blobs in the build with
the appropriate bit set in the Type encoding.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da)
BUG=none
BRANCH=none
TEST=none
Change-Id: I0366e548ab618a2200403b1262451727c095916c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4b9b41c47
Original-Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18991
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462954
This patch currently contains the SA initialization
required for bootblock phase -
1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I73657150cda113d27ccac3952d5ec05cd642e5fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7952e283fb
Original-Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18567
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/462953
This patch currently contains the SA initialization
required for bootblock phase -
1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id56ece7a40ce573846a642c4b08d37fcadc75107
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93ebe499d4
Original-Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18566
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462952
Create common Intel systemagent code.
This code currently contains the SA initialization
required in Bootblock phase, which has the following programming-
* Set PCIEXBAR
* Clear TSEG register
More code will get added up in the subsequent phases.
BUG=none
BRANCH=none
TEST=none
Change-Id: I246bc9298a0bc25304ee57e909ffa8993b7e0074
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01ae11b057
Original-Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18565
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462951
This patch to make common PCI device name between APL and SKL.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic74d1c1708285500210be34c3c2b71c4b90404f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ee54db246
Original-Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18576
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462950
This patch currently contains common CAR initialization
required in bootblock phase along with common MSR header -
1. Use SOC_INTEL_COMMON_BLOCK_CAR to have common CAR initialization
and CAR teardown.
2. Use common MSR header "intelblocks/msr.h" inside soc/cpu.h
BUG=none
BRANCH=none
TEST=none
Change-Id: I24e83349bc89c2793f1a3376fdf7796d7d641800
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc4c7d8320
Original-Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18555
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462949
Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: I77457b06542cce1d5aa547a0fd9120e6966982ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03e971cd23
Original-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18381
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462948
To gradually consolidate and improve AGESA board romstages,
fork the original CAR setup code as a separate file. It becomes
too messy with preprocessor to attempt make changes within the
same file, and at end of patchset original becomes obsolete.
BUG=none
BRANCH=none
TEST=none
Change-Id: If6b072173e1cefc4f676f0295040ff6debeaeaa3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77d3c4b690
Original-Change-Id: I256b675b1ab9e13c2bcc956e0d67c6c03e91f2ed
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18620
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462939
We define AGESA_LEGACY as an implementation of mainboard
that has its romstage main completely under mainboard/
directory. We have learnt from other platforms this approach
has several downsides when it comes to making platform-wide
improvements.
We start by creating per-family romstage.c file, which
boards will gradually take into use by removing the
AGESA_LEGACY Kconfig option we here apply to all of them.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ff98b2ee71ee55883efe83372494d2181785388
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 967d94d626
Original-Change-Id: Id01931e185a023039a60af16a678de9966db8d65
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18619
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/462938
This board has a socketed SOIC-8 4 MB flash chip. All the flash
regions are unlocked by default but unfortunately flashrom
doesn't work with the original firmware and the stock UEFI flash
tool refuses to flash the coreboot image (different image ID).
For now, the external programmer seems to be the only option for
the first coreboot flashing.
Tested and working:
* Debian GNU/Linux Stretch (with Linux kernel 4.9, SeaBIOS)
* Microsoft Windows 7 installer with VGA blob (SeaBIOS)
* Internal GPU, both with VGA blob and libgfxinit (VGA and DVI)
* External GPU
* RAM (tested 8 + 8 GB)
* S3
* USB, both the 2.0 and 3.0 ports
* Sata
* Thermal management
* Sound
* LAN
* Bluetooth
* VT-x and VT-d
* me_cleaner
Not working:
* Microsoft Windows 7 installer with libgfxinit
Untested:
* Backside Mini PCI-E port
* DisplayPort and HDMI ports
Issues:
* The USB is always powered, even is S3 and S5 (like in the
original firmware).
* Internal flashing with flashrom doesn't work after resuming
from S3.
* The raminit is unreliable, as the RAM training sometimes fails
and sometimes succeeds, with the same couple of RAMs. Once
a MRC cache has been created, the raminit works fine.
* If an external card is inserted and the option
ONBOARD_VGA_IS_PRIMARY is not enabled, the internal GPU
disappears completely from the PCI bus.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5dfe408289bca6647c228b5e1ca17688723c535a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1bea5b7df2
Original-Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18564
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/462937
This chip is similar to the Fintek F71869AD.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic48309e90c4356e1689797de7d5e5edefe999134
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2fca86f370
Original-Change-Id: Iba3f3dadf2b15071981f52d0b08da7847354bd23
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18563
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/462936
This is a cosmetic change.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4536ce41bad5c02a10d008b52df66819b0910bd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50db9c99be
Original-Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18960
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/462935
The pre-CQ doesn't really do its job very well for firmware at the
moment, since it only runs a couple of boards and misses a lot of our
mainboard-specific code. This patch is an attempt to improve this by
manually specifying a list of recent boards that are most likely to
break from new patches. This list will have to be continuously updated
as we are adding new baseboards.
BRANCH=none
BUG=chromium:701504
TEST=none
Change-Id: I14cec82484e36b4163a33a485893b92ecd0a8c32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455118
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Don Garrett <dgarrett@chromium.org>
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are
linked directly into the bootblock or the romstage. However, they're
still compiled with a separate "libverstage" source file class, linked
into an intermediate library and then linked into the final destination
stage.
There is no obvious benefit to doing it this way and it's unclear why it
was chosen in the first place... there are, however, obvious
disadvantages: it can result in code that is used by both libverstage
and the host stage to occur twice in the output binary. It also means
that libverstage files have their separate compiler flags that are not
necessarily aligned with the host stage, which can lead to weird effects
like <rules.h> macros not being set the way you would expect. In fact,
VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86
because their libverstage code that gets compiled into the romstage sets
ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to
run pre-migration.
This patch resolves these problems by removing the separate library.
There is no more difference between the 'verstage' and 'libverstage'
classes, and the source files added to them are just treated the same
way a bootblock or romstage source files in configurations where the
verstage is linked into either of these respective stages (allowing for
the normal object code deduplication and causing those files to be
compiled with the same flags as the host stage's files).
Tested this whole series by booting a Kevin, an Elm (both with and
without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode.
Change-Id: I48be3be92c154c5c93e7696e39d1d65773fc6c5f
Original-Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4
Original-Reviewed-on: https://review.coreboot.org/18302
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: e91d170d21
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462015
This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I45230f7a73521d66fdc46a54ee9bde32b3e7eae7
Original-Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Original-Reviewed-on: https://review.coreboot.org/18984
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: 58c3938705
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462014
No board has ever tried to combine CONFIG_SEPARATE_VERSTAGE with
CONFIG_VBOOT_STARTS_IN_ROMSTAGE. There are probably many reasons why
this wouldn't work (e.g. x86 CAR migration logic currently always
assumes verstage code to run pre-migration). It would also not really
make sense: the reason we use separate verstages is to decrease
bootblock size (mitigating the boot speed cost of slow boot ROM SPI
drivers) and to allow the SRAM-saving RETURN_FROM_VERSTAGE trick,
neither of which would apply to the after-romstage case. It is better to
just forbid that case explicitly and give programmers more guarantees
about what the verstage is (e.g. now the assumption that it runs pre-RAM
is always valid).
Since Kconfig dependencies aren't always guaranteed in the face of
'select' statements, also add some explicit compile-time assertions to
the vboot code. We can simplify some of the loader logic which now no
longer needs to provide for the forbidden case. In addition, also try to
make some of the loader logic more readable by writing it in a more
functional style that allows us to put more assertions about which cases
should be unreachable in there, which will hopefully make it more robust
and fail-fast with future changes (e.g. addition of new stages).
Change-Id: Ibf115ba8ac3238bb9f87cafbfde236cd4f555d11
Original-Change-Id: Iaf60040af4eff711d9b80ee0e5950ce05958b3aa
Original-Reviewed-on: https://review.coreboot.org/18983
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Commit-Id: 73d042bd90
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462013
