Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).
(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)
Change-Id: Ie50b79b1bb1acd10ed64332eaa763f0a6cb9ea17
Original-Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Original-Reviewed-on: https://review.coreboot.org/19022
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: 1210b41283
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462007
The correct way to mock out vboot TPM accesses these days is the
CONFIG_VBOOT_MOCK_SECDATA Kconfig option. There are some remnants of
older TPM-mocking infrastructure in our codebase that are as far as I
can tell inert. Remove them.
Change-Id: I62e2c58a2d8796f43690ca3525074caa4977bde1
Original-Change-Id: I3e00c94b71d53676e6c796e0bec0f3db67c78e34
Original-Reviewed-on: https://review.coreboot.org/18977
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Commit-Id: 84b2978ed6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462006
Due to an unfortunate race between adding verstage support and reverting
an earlier hack that disabled the optimized assembly versions of
memcpy(), memmove() and memset() on ARM64, it seems that we never
enabled the optimized code for the verstage. This should be fixed so
that all stages use the same architecture support code.
Change-Id: I97547ed22f6522ba1eaaaf8bb857d57e247fbe34
Original-Change-Id: I0bf3245e346105492030f4b133729c4d11bdb3ff
Original-Reviewed-on: https://review.coreboot.org/18976
Original-Tested-by: build bot (Jenkins)
Original-Commit-Id: 2f891a08e7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462005
Instead of defining a separate LID device for mainboards using
chromeec, define EC_ENABLE_LID_SWITCH for these boards.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3f68109701dc74fe44f5d35fdbfe44e2bfd1b4e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5029a1668e
Original-Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18964
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/459510
Instead of defining SIO_EC_ENABLE_PS2K by default for all boards and
doing an undef in variant/onboard.h, move the definition of
SIO_EC_ENABLE_PS2K to variant/onboard.h. This avoids dependency
between different *.asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id20f7df9985490f42ace4b5dbf03d7c5e8ff84ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3795b03b69
Original-Change-Id: I83e4ce42a594e952a443c618d7ef9840113027b9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18965
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/459508
Replace the use of the old device_t definition inside
soc/intel/fsp_baytrail.
BUG=none
BRANCH=none
TEST=none
Change-Id: I208de00fab4cefe1e35b26f2ece16117750de2e4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb94dcf5d5
Original-Change-Id: I2791346289c04049e6f032c8e120e4be9ba6657f
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/17319
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459507
- Change preprocessor #if to standard C if. This will get optimized
out if the config option is disabled, but lets the compiler check the
contents.
- CONFIG_USBDEBUG is always going to be defined even if it's disabled,
so this check is not going to work as expected.
See the coreboot Kconfig documentation in /Documentation/core/Kconfig.md
BUG=none
BRANCH=none
TEST=none
Change-Id: I57ae98d60f240b92d1e2fd9146c95c2928631db5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5ef5c00704
Original-Change-Id: Ia63438d9525e79307d9229ad3ffa2962978611d8
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18974
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/459506
Currently the `break` further down is called unconditionally as the
brackets for the body of the if statement are missing. Add those.
BUG=none
BRANCH=none
TEST=none
Change-Id: I738178ea9f4f92fad237cfec23acad6af17995dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b45bbb253f
Original-Change-Id: I34917a9877dcc882d880dedea689e1d72fe52888
Original-Found-by: Coverity (CID 1372941: Control flow issues (UNREACHABLE))
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18971
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459504
Also move all local variable declaration at starting of function
block.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie2e4ef0cac7545cb8acc6d3513cbe364065b19bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c790850ebe
Original-Change-Id: I774485a23b4b7d96a8dbd837da45553251dff3b0
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18949
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/459503
1. Remove CPU throttling effect of the charger sensor
Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
2. Change TSR1 influence from 200 to 100
3. Change TSR2 sample period from 120s to 30s
BUG=b:35585781
BRANCH=reef
TEST=built, and verified on snappy by thermal team.
Change-Id: Ic0e9b9c76a6cf56b6fc07e483a78f44665f4d949
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccc21ca685
Original-Change-Id: Ic3fc51c4288b24f4e64950e5b148aed4495a1c3b
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18950
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/459501
The upcoming Cr50 firmware changes will require the AP to enable the
previously downloaded Cr50 firmware update(s).
A new vendor command (TPM2_CR50_SUB_CMD_TURN_UPDATE_ON) is used for
that. The command accepts one parameter - a timeout value in range of
0 to 1000 ms.
When processing the command the Cr50 checks if the alternative RO or
RW image(s) need to be enabled, and if so - enables them and returns
to the host the number of enabled headers.
If the vendor command requested a non-zero timeout, the Cr50 starts
a timer to trigger system reboot after the requested timeout expires.
The host acts on the number of enabled headers - if the number is
nonzero, the host prepares the device to be reset and waits for the
Cr50 to reboot the device after timeout expires.
This patch also adds more formal vendor command
marshaling/unmarshaling to make future additions easier.
BRANCH=gru,reef
BUG=b:35580805
TEST=with the actual user of this code in the next patch verified that
the cr50 update is enabled as expected.
Change-Id: I06feba1e778d20fdc70038672d663d6236a3e180
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 021ec2819b
Original-Change-Id: Ic76d384d637c0eeaad206e0a8242cbb8e2b19b37
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18945
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/459670
Creating google/fizz directory based on poppy (using kabylake and FSP
2.0). Only making name changes and Copyright year changes. Many
poppy-specific configs left in and will be updated in follup CLs.
BUG=b:35775024
BRANCH=None
TEST=Compile fizz board
Change-Id: Ic40bb336dabc4bf48213ccd454d29032c5846bc9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 243dc3913d
Original-Change-Id: Icab3639a53fef65e904e797028916fda879fff7c
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18796
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459665
This patch implements SGX initialization steps in coreboot per Intel SGX
BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC
capability and PRM (processor reserved memory) of desired size (needs to
be configured through PrmrrSize) are provisioned for later software
stack to use SGX (i.e., run SGX enclaves).
One issue is still puzzling and needs to be addressed: by calling
configure_sgx() in cpu_core_init() which is the per-thread function, SGX
is always failing for thread 0 but is successful for other 3 threads.
I had to call configure_sgx() again from soc_init_cpus() which is the
BSP-only function to make it enable on the BSP.
Another pending work is the implementation for the Owner Epoch update
which shall be added later.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified SGX activation is successful on all threads.
Change-Id: I3bca7131d5f51a7bdb913cc6ae135b910d3aa52e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7de031759b
Original-Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18445
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/459664
Replace the use of the old device_t definition inside
mainboard/samsung/stumpy.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibf85e77a6901fab095c06798ea16b6424f4bb776
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9709af3521
Original-Change-Id: Ie6209b3b40d9aad0723690e7aeb3edfd0bfcc4a8
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/17304
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459661
Replace the use of the old device_t definition inside
mainboard/samsung/lumpy.
BUG=none
BRANCH=none
TEST=none
Change-Id: I45bd8786ba4341f123264b2fbed8747447c8d4bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b542faf20
Original-Change-Id: I39fe6bad42b3b0772d09d0fa7af357b797b8e04f
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/17303
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459660
Replace the use of the old device_t definition inside
northbridge/via/vx900.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaf6a189371992a2f6d391802c1bb714d29baf8ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 823f7bb962
Original-Change-Id: I04292a6b698a42a5c582eddcef7cf5a235e1a464
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/17317
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459659
Replace the use of the old device_t definition inside
mainboard/technexion/tim5690.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71904345f76418c71cd37d29f5078e142c1b8678
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a34e70e002
Original-Change-Id: I661daa5ab34c70db8ed783e5bf1114877f13b548
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/17307
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459658
FSP disables host access to shadowed PMC XRAM registers by default,
it also provides a UPD to enable/disable host reads to these regiters.
Expose the same in devicetree as a config option.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1ffd08c2aa4abb52787ae7b8c91cbc734290f6ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ffe58107df
Original-Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18319
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/458355
It makes no sense to read SPDs if the system will reset anyway.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icc0587de64d04063c9203535a773ec1967604b23
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb5e77c478
Original-Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17661
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/458348
Currently, its impossible for the user to select `NO_POST`, for boards
selecting `CONSOLE_POST` in their config.
```
warning: (BOARD_SPECIFIC_OPTIONS) selects CONSOLE_POST which has unmet
direct dependencies (VENDOR_SIEMENS && BOARD_SIEMENS_MC_BDX1 || !NO_POST)
```
This is currently done for Intel Camelback Mountain and Siemens MC-BDX1.
Selecting the option `CONSOLE_POST` in board specific configuration is
not a good idea, as this should be user configurable over Kconfig, and
also the tree-wide defaults should be the same for these options.
Kconfig is different, as commit 97535558f1 (mainboard/{google,intel}:
Change config option selection) only touch the Intel board.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie93d38b3c82261458534993b856737f9ea5d019c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 98adaf5989
Original-Change-Id: I91c1e0cb92ed218b6bbc7c33759b91f748cf6f51
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18878
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/458346
Currently, its impossible for the user to select `NO_POST`, for boards
selecting it in their config.
```
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS) selects POST_IO which has unmet direct
dependencies (VENDOR_ASUS && (BOARD_ASUS_F2A85_M ||
BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE) && (BOARD_ASUS_F2A85_M
|| BOARD_ASUS_F2A85_M_PRO) || VENDOR_MSI && BOARD_MSI_MS7721 ||
PC80_SYSTEM && !NO_POST)
```
This is currently done for Intel Mohon Peak, and its descendants.
Selecting the option `POST_IO` in board specific configuration is not a
good idea, as this should be user configurable over Kconfig, and also
the tree-wide defaults should be the same for these options.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7e000a03e572cc537ee2d75b4a9a50862bff0c0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 237ca0d20c
Original-Change-Id: Ia4ab0d942b7d66f18466a770ef739109ab0db629
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18877
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/458345
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB
and use common function dimm_info_fill() to save it in CBMEM.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot Reef to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".
Change-Id: Iab860b9eefd2e26776a4aff50e69edec3999d963
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad017c63d2
Original-Change-Id: I33c3a0bebf33c53beadd745bc3d991e1e51050b7
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18451
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/458343
The Lenovo H8 battery interface uses a paged EC memory area.
Some Thinkpads (in particular the S230U) use a different EC controller
(ENE KB9012) with mostly compatible firmware, which requires an explicit
delay between writing the page register and reading the page data.
BUG=none
BRANCH=none
TEST=none
Change-Id: I96cb81547b5fa58528d586121ce0e1c2eaf09c11
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1583dbd7b7
Original-Change-Id: Iaeb8c4829efa29139396b519de803f10dd93f03f
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/18348
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/458342
We just support Raydium touchscreen instead of Elan.
Thus we have to remove Elan touchscreen device
and add Raydium touchsrcreen device.
BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot
Change-Id: Id11fd45074ad51a282c66e1565d88f82545e02e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b980d1ae80
Original-Change-Id: I7b33a29287dcb90e379b52cc93825f2988a0d3c9
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18789
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/458340
This is achieved by setting up Kconfig and Kconfig.name very similar
to how variants are used.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8a1bb508157beb7220f16d87144a71b3decfbc59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1dfc0a64d4
Original-Change-Id: I22089ff29e3879d7956527a092a0ac6425b05cb3
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17894
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/458338
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
ERROR: Macros with complex values should be enclosed in parentheses
ERROR: switch and case should be at the same indent
WARNING: char * array declaration might be better as static const
WARNING: else is not generally useful after a break or return
WARNING: storage class should be at the beginning of the declaration
WARNING: void function return statements are not generally useful
WARNING: break is not useful after a goto or return
WARNING: Single statement macros should not use a do {} while (0) loop
WARNING: sizeof *t should be sizeof(*t)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I962c3ac9554b2205b15734747542d59894edae65
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b5678f21f
Original-Change-Id: I39d49790c5eaeedec5051e1fab0b1279275f6e7f
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18865
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/458337
1. correct DPTF TCHG target device to TSR2
2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
BUG=b:35586881
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18920
Tested-by: build bot (Jenkins)
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457911
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Since SD card controller is expected to enter D3hot by runtime power
management if there is no card inserted, we need to use a sideband IRQ
pin which is not under the control of the controller. Thus, configure
GPP_A7 as the sideband IRQ pin and pass it to OS as the card detect
pin.
BUG=b:35586693
BRANCH=None
TEST=Verified on a reworked poppy board that card detect works fine.
Change-Id: I4512f5d7829583e27c9750463396eaffbc5702b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18926
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/457910
We have code for certain Veyron variant names that were either never
made into an actual board (Gus, Nicky, Thea) or used for Google-internal
test boards that no longer exist (Pinky, Shark). Let's clean them out to
avoid confusing people.
BUG=none
BRANCH=none
TEST=none
Change-Id: I60a7f1da4d468efdd2efced5d4e3e87599cc87fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7504268318
Original-Change-Id: Icdce5f0f3613e089d0994318b02dba54170f0c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18860
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/457060
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Change hid name to "WDHT0002" for Weida WDT8752 which is supported by
standard hid i2c Linux driver.
BUG=b:35586513
BRANCH=reef
TEST=build, boot on snappy, and verified acpi node "WDHT0002" created.
Change-Id: Icdaacbdf9589b201133a2e04f3e842fdc4df0ae7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41dded3548
Original-Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18874
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/457368
It's not relevant to throttle CPU based on the charger sensor.
So, remove this CPU throttling effect.
BUG=b:35908799
BRANCH=master
TEST=Built and booted on Electro DUT
Change-Id: I456f90a47d4c6c183517c0dd8e1673f672283848
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8c891a15a
Original-Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18852
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/457367
Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
In case something goes wrong on one of the
cpus, add the ability to use a barrier with
timeout so that other cpus don't wait forever.
Remove static from barrier wait and release.
BUG=chrome-os-partner:59875
BRANCH=reef
TEST=None
Change-Id: I51079396aa35bcebb5282e30ecf2235d9694b512
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9b76f0b27b
Original-Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24
Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18107
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/457366
Some SSE instructions could take 128bit memory operands from
stack.
AGESA vendorcode was always built with SSE enabled, but until
now stack alignment was not known to cause major issues. Seems
like GCC-6.3 more likely emits instructions that depend on the
16 byte alignment of stack.
BUG=none
BRANCH=none
TEST=none
Change-Id: I58ae02a2204f426b89f892a0421f916711bd91f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4796c32ad6
Original-Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18823
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457365
This reuses some of gm45 code to set up the panel.
Panel start and stop delays and pwm frequency can now be set in
devicetree.
Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.
The core display clock is computed according to "Mobile Intel 945
Express Chipset Family" Datasheet.
This selects Legacy backlight mode since most targets have some smm
code that rely on this.
This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.
A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.
BUG=none
BRANCH=none
TEST=none
Change-Id: I86445ab53cb83bc5183fb998ca03e00b4746a33f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e079000dc
Original-Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18141
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/457362
Fix the following error and warnings detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I9468d58e4f996d77825f6cd9b99081bc240d109e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 216712ae01
Original-Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18886
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/457361
Fix the following error and warnings detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
WARNING: line over 80 characters
WARNING: storage class should be at the beginning of the declaration
WARNING: adding a line without newline at end of file
WARNING: __func__ should be used instead of gcc specific __FUNCTION__
WARNING: Comparisons should place the constant on the right side of the test
TEST=None
Change-Id: I2c6d82f94ec6bce84913452a9eb227b3cbec5f31
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ef5192627
Original-Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18885
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457360
