Commit graph

19656 commits

Author SHA1 Message Date
Martin Roth
97a6776ac0 UPSTREAM: util/abuild: Add more error handling for command line options
- Show an error if a directory is added after the command line options
to catch scripts using the old parameters.
- If an invalid parameter is specified, show the parameter.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17741
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: Ie8948361f1c51e89a99bdb13df8c554747cd521d
Reviewed-on: https://chromium-review.googlesource.com/419626
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:31 -08:00
Martin Roth
7f66f08b3e UPSTREAM: util/abuild: Add argument -R to specify root directory
cbroot was previously specified by just adding it to the end of the
command line with no explicit identifier.  This change allows it to
go anywhere in the command line and adds the -R or --root identifier.

This makes the command line more consistent.  Most of the time, this
argument isn't even needed, as the automatic detection finds cbroot.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17740
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I1d6fd8f51765d0d8b29be8af1e8105e06dd44cc8
Reviewed-on: https://chromium-review.googlesource.com/419625
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:28 -08:00
Martin Roth
f006346951 UPSTREAM: util/abuild: Clean up usage
- Indent with spaces for consistency
- Change lbroot to cbroot
- Remove incomplete list of options from usage line
- Capitalize first word of all option text
- Alphabetize options other than version and help
- Move version and help options to the end

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17724
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: Id5bd4db8d7e3705cbbb93895a46a3608cd1b09e2
Reviewed-on: https://chromium-review.googlesource.com/419624
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:26 -08:00
Martin Roth
f9e482254e UPSTREAM: util/abuild: Fix or disable shellcheck warnings
This cleans up the shellcheck warnings in abuild.

Warning count:
1 Unexpected ==.
1 Use "${var:?}" to ensure this never expands to / .
1 VARIABLE appears unused. Verify it or export it.
1 Use "$@" (with quotes) to prevent whitespace problems.
2 Consider using { cmd1; cmd2; } >> file instead of individual redirects.
2 Expressions don't expand in single quotes, use double quotes for that.
3 Prefer [ p ] || [ q ] as [ p -o q ] is not well defined.
4 $/${} is unnecessary on arithmetic variables.
5 Check exit code directly with 'if mycmd;', not indirectly with $?.
5 Use cd ... || exit in case cd fails.
11 Declare and assign separately to avoid masking return values.
13 Use $(..) instead of legacy `..`.
20 Don't use variables in the printf format string.
104 Double quote to prevent globbing.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17722
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I9c77e122435ba87ce3a4aee76b5022f7265f9ef2
Reviewed-on: https://chromium-review.googlesource.com/419623
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:24 -08:00
Furquan Shaikh
4ba538e2a2 UPSTREAM: drivers/intel/fsp2_0: Include stddef.h in soc_binding.h
soc_binding.h includes FSP headers which define NULL macro. Because of
this, including stddef.h after soc_binding.h results in NULL being
re-defined. Thus, include stddef.h in soc_binding.h to avoid having
users include stddef.h along with soc_binding.h.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17773
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa
Reviewed-on: https://chromium-review.googlesource.com/419622
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:21 -08:00
Arthur Heymans
44c75bd604 UPSTREAM: nb/intel/i945: Make pci_mmio_size a devicetree parameter
Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.

A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Reviewed-on: https://chromium-review.googlesource.com/419621
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:19 -08:00
Kyösti Mälkki
2ad8d89ca4 UPSTREAM: ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP default
Except fo nehalem, K8, f10 and f15 (non-AGESA) romstage ramstack
is placed in CBMEM and ramstage loader takes care of tiny backup.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17358
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I8477944f48ed2493d0a5e436a4088eb9fc3d59c5
Reviewed-on: https://chromium-review.googlesource.com/419620
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:16 -08:00
Kyösti Mälkki
9255e1c35f UPSTREAM: ACPI S3: Hide acpi_slp_type
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/10360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I48a20e34f11adc7c61d0ce6b3c005dbd712fbcac
Reviewed-on: https://chromium-review.googlesource.com/419619
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:14 -08:00
Kyösti Mälkki
02326a0dea UPSTREAM: intel/nehalem: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17676
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566
Reviewed-on: https://chromium-review.googlesource.com/419618
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:12 -08:00
Kyösti Mälkki
21a55a0758 UPSTREAM: intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGE
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2085fc3a17d32cfbdab9ec0b7afbc01031e75b47
Reviewed-on: https://chromium-review.googlesource.com/419617
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:09 -08:00
Kyösti Mälkki
ee253069a3 UPSTREAM: intel/i945: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Scratchpad register was read too
late in ramstage so acpi_is_wakeup_s3() did not evaluate
correctly.

This fixes low memory corruption at 0x1000-0x102c and the lack
of coreboot tables (util/cbmem not working) after S3 resume.

This also fixes console log from reporting early in ramstage
"Normal boot" while on "S3 resume" path.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705
Reviewed-on: https://chromium-review.googlesource.com/419616
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:07 -08:00
Kyösti Mälkki
c1462e1263 UPSTREAM: intel/gm45: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695
Reviewed-on: https://chromium-review.googlesource.com/419615
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:04 -08:00
Kyösti Mälkki
6fe5716f13 UPSTREAM: intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup
Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Reviewed-on: https://chromium-review.googlesource.com/418874
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:02 -08:00
Kyösti Mälkki
2d29b5f3f5 UPSTREAM: intel i945 gm45 x4x: Apply cbmem_top() alignment
Force modest 4 MiB alignment to help with MTRR assignment.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17780
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I49a7d1288bc079da1b8bd52150ddcfcfe2e51179
Reviewed-on: https://chromium-review.googlesource.com/418873
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:00 -08:00
Kyösti Mälkki
5604e16494 UPSTREAM: x86 SMM: Fix use with RELOCATABLE_RAMSTAGE
The value for _size was not evaluated correctly if ramstage
is relocated, make the calculation runtime.

While touching it, move symbol declarations to header file.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2
Reviewed-on: https://chromium-review.googlesource.com/418872
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:48:57 -08:00
Arthur Heymans
797e43639e UPSTREAM: cpu/intel/lga775: Do not select model_6ex CPU
Model 6ex are Core Solo and Core Duo CPUs (yonah) that never existed
with a LGA775 socket.

This reduces the size of the microcode from 180k to 168k.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17120
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Ic5b3d0e7c8009dab2dca477010c328274a818fed
Reviewed-on: https://chromium-review.googlesource.com/418961
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10 18:20:37 -08:00
Pratik Prajapati
9ab5cfbdb1 UPSTREAM: cbfs: Add API to locate a file from specific region
This patch adds an API to find file by name from
any specific region of fmap.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iabe785a6434937be6a57c7009882a0d68f6c8ad4
Reviewed-on: https://chromium-review.googlesource.com/418960
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10 18:20:34 -08:00
Kyösti Mälkki
667f34ce6d UPSTREAM: intel 82801dx/gx/ix: Commit SMM relocation code to DRAM
Make sure relocation code reaches DRAM before issuing any
SMIs. Snooping and cache coherency may have undefined
behaviour as CPUs do not have uniform MTRR layout yet.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17712
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac
Reviewed-on: https://chromium-review.googlesource.com/418959
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10 18:20:32 -08:00
Kyösti Mälkki
04d540a03f UPSTREAM: postcar_loader: Support LATE_CBMEM_INIT boards
Create postcar_frame object without placing stack in CBMEM.
This way same cache_as_ram.inc code can be used unmodified.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ic5ed404ce268ee881e9893dd434534231aa2bc88
Reviewed-on: https://chromium-review.googlesource.com/418958
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10 18:20:30 -08:00
Kyösti Mälkki
57d76eea0a UPSTREAM: intel/sandybridge: Use postcar_frame for MTRR setup
Adapt implementation from skylake.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db
Reviewed-on: https://chromium-review.googlesource.com/418957
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10 18:20:27 -08:00
Aaron Durbin
a15cc0658e UPSTREAM: mainboard/google/reef: fill in NHLT ACPI OEM header fields
Fill in the NHLT ACPI OEM header fields to differentiate
different audio solutions on a per board basis. This handles
boards that share a firmware that are differentiated by
the SKU id and boards that have their own firmware. For the
latter, the Oem Table ID uses the VARIANT_DIR to differentiate.
"reef" is always used for Oem ID which is treated as more of
family in this case.

iasl -d shows the following on reef:
[00Ah 0010   6]                       Oem ID : "reef"
[010h 0016   8]                 Oem Table ID : "reef"
[018h 0024   4]                 Oem Revision : 00000008

BUG=chrome-os-partner:60494
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17772
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76
Reviewed-on: https://chromium-review.googlesource.com/418956
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10 18:20:25 -08:00
Aaron Durbin
ff7ae57046 UPSTREAM: mainboard/google/reef: add board SKU'ing support
There are 2 gpios on reef-like boards that can be composed
into a SKU. Add support for identifying the SKU value using
the base 3 gpio logic. Also export the SKU information to the
SMBIOS type 1 table.

BUG=chrome-os-partner:59887,chrome-os-partner:60494
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17771
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239
Reviewed-on: https://chromium-review.googlesource.com/418955
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10 14:55:41 -08:00
Ziyuan Xu
e6eb1f5637 rockchip: rk3399: change emmc clk to 148.5MHz
Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could
improve stability like kernel.

CQ-DEPEND=CL:386527
BUG=chrome-os-partner:54377
BRANCH=none
TEST=build and boot on kevin

Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/386865
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-12-10 01:14:11 -08:00
Patrick Georgi
e8a88bf744 vendorcode/google/chromeos: zero out SHARED_DATA region
BUG=chromium:595715
BRANCH=none
TEST=/build/$board/firmware/coreboot.rom has a zeroed out SHARED_DATA
region if it exists.

Change-Id: I0b59f1f0e2f8645000f83cb3ca7f49e4da726341
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/417821
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2016-12-09 21:48:22 -08:00
Patrick Georgi
d2e3be81fa vendorcode/google/chromeos: Fill in firmware ID regions
Chrome OS images have three firmware ID regions, to store version
information for the read-only and the two read-write areas. Fill them
with a suitable default and allow configuring a different scheme.

There's already an override in google/foster and google/rotor to match
the naming scheme used so far (in depthcharge).

BUG=chromium:595715
BRANCH=none
TEST=/build/$board/firmware/coreboot.rom has the expected values in the
regions.

Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/417320
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2016-12-09 21:48:19 -08:00
Patrick Georgi
baf378c5f2 util/cbfstool: Enable filling fmap regions with a given value
So far, cbfstool write, when used with the -u/-d options (to "fill
upwards/downwards") left the parts of the region alone for which there
was no new data to write.

When adding -i [0..255], these parts are overwritten with the given
value.

BUG=chromium:595715
BRANCH=none
TEST=cbfstool write -u -i 0 ... does the right thing (fill the unused
space with zeroes)

Change-Id: I3752f731f8e6592b1a390ab565aa56e6b7de6765
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/417319
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2016-12-09 10:49:44 -08:00
Martin Roth
01ff9e24f6 UPSTREAM: abuild: Build saved config files
Update abuild to allow for building saved miniconfig files.

If one or more config files exist for a platform under
coreboot/configs, they will be built instead of the automatically
generated default config.

The config filename needs to start with "config.$VENDOR_$BOARD" to be
picked up by the abuild script.

- Update to version 0.10.0
- Add -d parameter to specify the saved config file directory
- Break 2nd half of create_config function into update_config
to set the payload for saved config files.
- Unset new payload Kconfig options that could be set in a saved
config file.
- Update a bunch of MAINBOARD variable names to BUILD_NAME since
the build name isn't necessarily the same as the mainboard name.
- Split build_target into two functions - build_target and
build_config because one mainboard can now build multiple
configurations.
- Update remove target and call it directly from build_target()
instead of from build_targets()

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17590
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I1a276d3e507b178f7dcd9dc125fa9c59f1ab47bd
Reviewed-on: https://chromium-review.googlesource.com/418445
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:30:13 -08:00
Martin Roth
90ee62e947 UPSTREAM: util/kconfig/conf.c: Fix newline in error printf
For some reason the \n in the defconfig save error was not escaped.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17742
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>

Change-Id: I6a76b258f461a194fe17aae2b4fa04326b46d8d6
Reviewed-on: https://chromium-review.googlesource.com/418444
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:30:11 -08:00
Martin Roth
7550586ec8 UPSTREAM: util/lint: Add check to verify saved configs are miniconfigs
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17600
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)

Change-Id: Ifc5ec645dd27663c1b1fde9ff16d48534606a554
Reviewed-on: https://chromium-review.googlesource.com/418443
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:30:09 -08:00
Martin Roth
5e89ac496d UPSTREAM: configs: Add some sample default configuration files
Test some config options that don't typically get tested.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17591
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Ie05c99411c8ce6462a6f5502b086ee2b72a4324b
Reviewed-on: https://chromium-review.googlesource.com/418442
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:30:06 -08:00
Duncan Laurie
450aa6ab3e UPSTREAM: google/eve: Add ASL code to describe SPI FPC1020 controller
There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.

BUG=chrome-os-partner:55538
BRANCH=None

TEST=successfully load fpc1020 kernel module on eve board

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Reviewed-on: https://chromium-review.googlesource.com/418441
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:30:04 -08:00
Andrey Petrov
af76db9fb1 UPSTREAM: soc/intel/apollolake: Move privilege drop to later stage
Previously privilege drop was happening "too early" and that caused some
PMC IPC programming (performed in FSP) to fail because sideband was
already locked out. This change set moves privilege drop to later stage,
after last FSP notify call.

BRANCH=reef
BUG=chrome-os-partner:60657
TEST=iotools rdmsr X 0x121, make sure they can't be read.
Also dmesg|grep -i IPC to make sure there are no errors related

Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17769
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7
Reviewed-on: https://chromium-review.googlesource.com/418440
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:30:02 -08:00
Aaron Durbin
94c26e603c UPSTREAM: cpu/x86: allow AP callbacks after MP init
There are circumstances where the APs need to run a piece of
code later in the boot flow. The current MP init just parks
the APs after MP init is completed so there's not an opportunity
to target running a piece of code on all the APs at a later time.
Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows
the APs to perform callbacks.

BUG=chrome-os-partner:60657
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17745
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>

Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6
Reviewed-on: https://chromium-review.googlesource.com/418439
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:59 -08:00
Aaron Durbin
4944047ed1 UPSTREAM: bootstate: add arch specific hook at coreboot exit
The bootstate machine allows one to schedule work at the
boundaries of each state. However, there are no priorities by
design. As such if there are things that need to be performed
that are interdependent between callbacks there's no way to
do that aside from explicitly putting the call in one of the
callbacks.

This situation arises around BS_OS_RESUME, BS_PAYLOAD_LOAD,
and BS_PAYLOAD_BOOT as those are the states where coreboot is
about to exit. As such, provide an architecture specific hook
at these key places so that one is guaranteed any work done
in arch_bootstate_coreboot_exit() is after all callbacks in
the state machine.

BUG=chrome-os-partner:60657
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17767
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Icb4afb341ab15af0670501b9d21799e564fb32c6
Reviewed-on: https://chromium-review.googlesource.com/418438
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:57 -08:00
Kyösti Mälkki
ace1c52268 UPSTREAM: buildsystem: Drop explicit (k)config.h includes
We have kconfig.h auto-included and it pulls config.h too.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17655
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da
Reviewed-on: https://chromium-review.googlesource.com/418437
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:54 -08:00
Sumeet Pawnikar
d94643368a UPSTREAM: mainboard/google/reef: Set PL2 override to 15000mW
This patch sets PL2 override value to 15W in RAPL registers.

BUG=chrome-os-partner:60535
BRANCH=None

TEST=Built, booted on reef and verified PL2 value.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17730
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef
Reviewed-on: https://chromium-review.googlesource.com/416683
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:52 -08:00
Sumeet Pawnikar
b1d99fa2f7 UPSTREAM: soc/intel/apollolake: Set PL2 in RAPL register
This patch sets the package power limit (PL2) value
in RAPL register.

BUG=chrome-os-partner:60535
BRANCH=None

TEST=Built, booted on reef and verified PL2 value.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f
Reviewed-on: https://chromium-review.googlesource.com/416682
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:50 -08:00
Aaron Durbin
349265e4fe UPSTREAM: commonlib: provide incoherent region device
The MRC cache uses an incoherent mechanism for updating the
cache contents in that it assumes memory mapped boot device
access for checking against latest data for update. However,
it uses another driver for updating the underlying storage
area.

In order to aid in moving the MRC cache over to using
region_devices for updates provide an implementation of
a region_device which performs reads and writes to different
region_devices so that different drivers can be used
transparently.

BUG=chrome-os-partner:56151
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17716
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I30e858245c30cbccd6313aff5ebecd3fd98d7302
Reviewed-on: https://chromium-review.googlesource.com/418436
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:47 -08:00
Aaron Durbin
5d4276f439 UPSTREAM: drivers/spi: provide a mechanism to obtain the SPI flash boot device
The MRC cache wants to be able to access the SPI flash boot device.
Allow an easy way to provide that so that there isn't duplicate
spi_flash objects representing the same device.

BUG=chrome-os-partner:56151
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17715
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: Iba92e8bb8a6060cdd327b10f5f8ec23ac61101e7
Reviewed-on: https://chromium-review.googlesource.com/418435
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:45 -08:00
Aaron Durbin
abf56875a5 UPSTREAM: lib: add region file support
The region file library is added to provide the underpinnings for
other libraries that support appending updates when the data changes.
The most recent written data is deemed the latest data associated
with that "file". A good example is the MRC cache which in a follow-up
patch utilizes this library.

BUG=chrome-os-partner:56151
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17713
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: Ic3caf1edbb6f11dbbe27181a87b7b19d1224fffa
Reviewed-on: https://chromium-review.googlesource.com/412954
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 03:29:43 -08:00
Aaron Durbin
91680ad35f UPSTREAM: lib/compute_ip_checksum: mark data buffer as const
compute_ip_checksum() doesn't manipulate the data it is passed.
Therefore, mark it as const.

BUG=chrome-os-partner:56151
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17714
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I54cff9695a886bacd6314aa441d96aaa7a991101
Reviewed-on: https://chromium-review.googlesource.com/418374
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:57 -08:00
Matt DeVillier
f0b7025a50 UPSTREAM: google/beltino, tidus: simplify led_power_on() function
Simplify set_power_led() by consolidating switch and setting values
as needed inline based on LED state.  Remove unnecesary function
param, includes for Tidus.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17744
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: I28e6fac5f8d7e2ff419002db714ce88697895faf
Reviewed-on: https://chromium-review.googlesource.com/418373
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:55 -08:00
Damien Zammit
ff39666fa6 UPSTREAM: drivers/r8168: Read default MAC address from CBFS
This driver applies to 10ec:8168

Previously, this driver resetted the nic and set a hardcoded
MAC address.  Now the driver reads a default MAC address
from CBFS in the form of a string:
echo -n "xx:xx:xx:xx:xx:xx" > macaddress
and store the macaddress file in CBFS with the same name.

TESTED on GA-G41M-ES2L and GA-945GCM-S2L:
       MAC address was detected

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17672
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: If1af91120fa3efca3f1406334a83ed1e59fbdaf9
Reviewed-on: https://chromium-review.googlesource.com/418372
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:52 -08:00
Nico Huber
53f6ebb55e UPSTREAM: libpayload: Add Cougar Point PCH's AHCI to whitelist
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17353
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ie8ca342a32323be4c26c236a5209052ec724317f
Reviewed-on: https://chromium-review.googlesource.com/418371
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:50 -08:00
Dennis Wassenberg
62c2b83937 UPSTREAM: nb/intel/sandybridge: Lock PAVPC
This makes CHIPSEC happy. We don't enable PAVP, but it shouldn't hurt
to lock it nevertheless.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17352
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I9428f0b6e8868832eb79f7aea24cbc7961c2aa8f
Reviewed-on: https://chromium-review.googlesource.com/418370
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:48 -08:00
Dennis Wassenberg
0e3aeb8938 UPSTREAM: sb/intel/bd82x6x: Add TCO_Lock in finalize step
CHIPSEC found that the TCO_Lock was not set.
This is used to prevent changing the TCO_EN bit.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I42364dbef2511e656662566cf94591e76c6847ed
Reviewed-on: https://chromium-review.googlesource.com/418369
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:45 -08:00
Matt DeVillier
16f018c02b UPSTREAM: soc/broadwell: set EM4/EM5 registers based on cdclk
The EM4/EM5 registers in the mini-HD audio device must be set based
on the GPU cdclk value in order for HDMI audio to function properly.
Add variables to save the correct values when initializing the GPU,
and accessor functions to retrieve them in order to set the registers
when initializing the mini-HD audio device.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17718
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba
Reviewed-on: https://chromium-review.googlesource.com/418368
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:43 -08:00
Matt DeVillier
aa4f2044b6 UPSTREAM: google/beltino: fix LED, simplify function for Tricky variant
Simplify set_power_led() by consolidating switch and setting values
as needed inline based on LED state.

Fix non-off LED polarity for Tricky using correct value from Chromium source

TEST: power on Tricky, observe LED lit / solid

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17719
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee
Reviewed-on: https://chromium-review.googlesource.com/418367
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:41 -08:00
Kyösti Mälkki
19710f8322 UPSTREAM: autoport: Fix romstage generator
Prototype changed here:
   e258b9a intel sandy/ivy: Improve DIMM replacement detection

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17711
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Id79238db2e497b9163f3bd1b1d5d4bc11fe4da9e
Reviewed-on: https://chromium-review.googlesource.com/418366
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:38 -08:00
Subrata Banik
4fdaced971 UPSTREAM: src/device: Get device structure by path type
Add helper function to find a device by path type
in the device tree.

BUG=None
BRANCH=None
TEST=None

Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Dhaval V Sharma <dhaval.v.sharma@intel.com>
Reviewed-on: https://review.coreboot.org/17731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I8846f63bd2488788ea3c7ab5154e7cf431a252bc
Reviewed-on: https://chromium-review.googlesource.com/418365
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:36 -08:00