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UPSTREAM: mainboard/google/reef: Set PL2 override to 15000mW

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This patch sets PL2 override value to 15W in RAPL registers.

BUG=chrome-os-partner:60535
BRANCH=None

TEST=Built, booted on reef and verified PL2 value.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17730
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef
Reviewed-on: https://chromium-review.googlesource.com/416683
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2016-12-05 16:56:15 +05:30 • committed by chrome-bot
parent b1d99fa2f7
commit d94643368a
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/reef/variants/baseboard/devicetree.cb
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@ -53,6 +53,8 @@ chip soc/intel/apollolake
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
register "tdp_pl2_override_mw" = "15000"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"