The rush_ryu board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16107
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ia3836ff8cade3009730543177a66736ae197572b
Reviewed-on: https://chromium-review.googlesource.com/368959
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The rush board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I0f77bb791491509da7bd9cf25050e01c2f734a2f
Reviewed-on: https://chromium-review.googlesource.com/368958
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of treating offsets relative to after the header make
the offsets relative to the in-memory mirror buffer. This
simplifies the logic in that all offsets are treated the same.
It also allows one to remove a global variable.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16098
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I42491e05755d414562b02b6f9ae47f5c357d2f8a
Reviewed-on: https://chromium-review.googlesource.com/368957
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A region_device can be used to represent the in-memory mirror
of the event log. The region_device infrastructure has builtin
bounds checking so there's no need to duplicate that. In addition,
it allows for removing much of the math juggling for the buffer
size, etc.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16097
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic7fe9466019640b449257c5905ed919ac522bb58
Reviewed-on: https://chromium-review.googlesource.com/368956
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's only 2 users of checking if the event buffer is cleared
to the EOL value. Each were passing pointers of the in-memory
mirror while also doing calculations for the size to check. Since
the in-memory mirror is one big buffer the only thing required
to know is the offset to start checking from. The check is always
done through the end of the buffer.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16096
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icd4a7edc74407d6578fc93e9eb533abd3aa17277
Reviewed-on: https://chromium-review.googlesource.com/368955
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The command line parameters for these modes haven't worked in two
years and nobody noticed. They're obviously not getting used, so
remove them.
TEST=Generate static.c before and after the change, verify they're
identical.
BUG=None
BRANCH=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16079
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I1d746fb53a2f232155f663f4debc447d53d4cf6b
Reviewed-on: https://chromium-review.googlesource.com/368952
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of having directories and file names hardcoded, pass in the full
path and filename of both the input and output files.
In the makefile, create variables for these values, and use them in
places that previously had the names and paths written out.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16078
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: Icb6f536547ce3193980ec5d60c786a29755c2813
Reviewed-on: https://chromium-review.googlesource.com/368290
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of forcing the hardcoded 'devicetree.cb' filename under the
mainboard directory, this allows mainboards to select a filename for
the devicetree file.
This allows mainboard variants that need to use different devicetree
files to live under the same directory.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12529
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I761e676ba5d5f70d1fb86656b528f63db169fcef
Reviewed-on: https://chromium-review.googlesource.com/368289
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Allocating a 15980-byte scratchpad on the stack when your default stack
size is set to 16KB is really not a great idea. We're regularly
overflowing into the end of our heap when using LZMA in libpayload, and
just happen not to notice it because the heap rarely gets filled up all
the way. Of course, since we always *have* a heap in libpayload, the
much saner solution is to just use it directly to allocate the
scratchpad rather than accidentally grow backwards into it anyway.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16089
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ibe4f02057a32bd156a126302178fa6fcab637d2c
Reviewed-on: https://chromium-review.googlesource.com/368287
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The elog_flash_erase() was only called to erase the entire
elog region in flash. Therefore, drop the parameters and
perform the full erase.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16094
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6590347ae60d407bc0df141e9196eb70532f8585
Reviewed-on: https://chromium-review.googlesource.com/368285
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There was a check against the next event offset against
the shrink size in elog_shrink(). However, all calls
to elog_shrink() were conditionalized on the next
event offset exceeding the full threshold. The shrink
size is set to the minimum of the full threshold and
a percentage of the elog region size. Therefore, it's
impossible for the next event offset to be less than
the shrink size because full threshold is always greater
than or equal to the shrink size.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16093
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie6ff106f1c53c15aa36a82223a235a7ac97fd8c7
Reviewed-on: https://chromium-review.googlesource.com/368284
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For the elog shrink case we log the number of bytes shrunk
from the event log. However, when clearing the log the
size recorded was the entire region size including the header
as well as the event region space. To be more consistent
mark the clearing event with the number of bytes actually
cleared out (excluding the header size).
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16092
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7c33da97bd29a90bfe975b1c6f148f181016f13f
Reviewed-on: https://chromium-review.googlesource.com/368283
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The gsmi_exec() expects the parameter to be a pointer
to the 32-bit register storage of the SMI save state.
The previous code was passing a pointer with the value
obtained from the saved-state -- not a pointer to the
storage of the register value. This bug causes gsmi
to not log events because it's interrogating the
parameter buffer itself as if it were a pointer.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16087
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I37981424f1414edad1456b31cad1b99020d57db6
Reviewed-on: https://chromium-review.googlesource.com/368281
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since RTC is now a Kconfig ensure RTC is selected on the
x86 chipsets which are in Chrome OS devices. This allows
the eventlog to have proper timestamps instead of all
zeros.
BUG=chrome-os-partner:55993
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b
Reviewed-on: https://chromium-review.googlesource.com/368280
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
List of changes done here in this patch
1. Remove CARD definition from EMMC and SD Card Controller in scs.asl
since _RMV method does not get evaluated while setting up removable
attribute in sysfs in kernel.
"cat /sys/block/mmcblk1/removable" this command always returns 0.
This CARD Device includes _ADR which follows SDIO Bus format. But,
SD/EMMC sits on PCI Bus.
Hence this CARD Device specific _ADR code is also not needed.
2. Remove Base Address for ACPI debug output memory buffer in
systemagent.asl as it is not getting used throughout the code.
BUG=none
BRANCH=none
TEST=Build and boot kunimitsu
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16068
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I29effaffdafcc21e26445ec3c54aedecdbc50274
Reviewed-on: https://chromium-review.googlesource.com/368277
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Program PIRQ Routing with correct values, as done by FSP, and also in
'soc/intel/skylake/romstage/pch.c' file. If not done, these values get
overridden by "0" during PxRC -> PIRQ programming in ramstage, in
'soc/intel/skylake/lpc.c' file pch_pirq_init()function.
BUG=none
BRANCH=none
TEST=Build and boot kunimitsu
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16044
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046
Reviewed-on: https://chromium-review.googlesource.com/368276
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Here is the list of items of code cleanup
1. Define TCO registers in smbus.h and not in pmc.h (as per EDS).
2. Include smbus.h wherever these TCO register defines were used.
3. Remove duplication of define in gpio_defs.h.
4. Remove unnecessary console.h include from memmap.h as no prints done.
5. Remove unnecessary comment from pch.c.
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu.
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16027
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b
Reviewed-on: https://chromium-review.googlesource.com/368275
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the CONFIG_CCACHE variable is NOT set, define the CCACHE variable as
blank on the Chrome EC make command line. This will overrride and
disable the CCACHE variable in the Chrome EC makefile.
BUG=None
BRANCH=None
TEST=None
Change-Id: I9492b3af2d6cb746ec285f0bc00bba019229fa17
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16035
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368783
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The ARM64 MMU code maintains a list of used ranges, to avoid mapping the
DMA buffer over the coreboot tables and things like that. Unfortunately,
the overlap with ranges in that list is checked with
(start1 >= start2 && start1 <= end2) || (end1 >= start2 && end1 <= end2)
which is not a full overlap check and misses the case where the second
region is completely contained within the first. This patch replaces
that code with a properly vetted primitive from Stack Overflow.
BRANCH=none
BUG=chrome-os-partner:54416
TEST=Observe how Kevin recovery screen now gets drawn at 10x the speed.
Change-Id: Ie4dd43afeb8a30fedc4da28ccc6ecce9589d23f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16075
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368782
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Instead of writing the first word of 6 "post code structs" where only
one exists (leading to 0xDEAD and 5 garbage words), write the correct
set.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ic0aefaf938f146b2461b99182db421a73743931c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1361054, #1361055, #1361056
Reviewed-on: https://review.coreboot.org/16058
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/368781
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This relieves caller from having to check if the parameter being passed
in is NULL.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ia24ca6f55d28f067d9be825078249e9bf82b1fe3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/368627
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This replaces all occurrences of a hardcoded vboot path to the
VBOOT_SOURCE variable, that may be overridden from the command line,
witch fallback to the source from 3rdparty.
BUG=None
BRANCH=None
TEST=None
Change-Id: I093657f526a8711866ad208589cc9a3f505cc825
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368625
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adding kabylake device ids for chip inits.
Skylake and Kabylak do not differ much, the intention
is to support both SoCs in the same code base.
BUG=None
BRANCH=None
TEST=None
Change-Id: I9f985ae9a0c066f1136eabcdf5ef1c849ef0c83a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16049
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368716
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable I2C bus 2 for early init so it can be used by vboot for TPM
communication for verifying the memory init code.
BUG=chrome-os-partner:53336
BRANCH=none
TEST=build and boot on reef
Change-Id: I6c8857665dbcf495d1ac4fa40b238cd74baa7097
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16059
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368715
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Generate an object to describe the coreboot table region in ACPI
with the HID "CORE0000" so it can be used by kernel drivers.
To keep track of the "CORE" HID usage add them to an enum and add
a function to generate the HID in AML: Name (_HID, "CORExxxx")
BUG=chromium:589817
BRANCH=none
TEST=build and boot on chell, dump SSDT to verify contents:
Device (CTBL)
{
Name (_HID, "CORE0000") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadOnly,
0x7AB84000, // Address Base
0x00008000, // Address Length
)
})
}
Change-Id: Ifa39e378eb1e7c00f03d8d213f52ff3cb9c17606
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16056
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/368714
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
The -b FSP_LOC argument to cbfstool is only valid for the COREBOOT
CBFS. Don't pass that value for all other CBFS regions.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ibc90f238214bdde4f4d3e0d49b1981413d130f1a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368713
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
If EC_GOOGLE_CHROMEEC is enabled, ensure that the EC is in correct mode
before running memory init. This saves additional memory training
required in recovery path because of reboot later in ramstage.
BUG=chrome-os-partner:54245
BRANCH=None
TEST=None
Change-Id: I95b25327e4ec8b3c8784dbd34ff150c8c82864ea
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16034
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368712
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
SD CLK and CLK_FB needs to be pulled down by 20K.
SD CD_N is active LOW, needs to be pulled up by 20K
SD WP pin is not connected for uSD cards, enable writes
by default by pulling low by 20K.
BUG=chrome-os-partner:54866
BRANCH=None
TEST=Test with uSD cards.
Change-Id: I613b56cedc5796f22ba4d9fdd52c09a33acd6fef
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://review.coreboot.org/16057
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368711
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
The first attempt of providing a options-for-region function to call
to determining a file's cbfstool options would work, but it means there
can only be one instance which has to handle all of the files that may
need an override. That logic can be problematic in impelementation.
Instead, provide a mechanism to target cbfstool options for a given
CBFS region where the implementation is tightly coupled in the build
system to where the file as requested to be added to cbfs. This allows
there to be a base set of cbfstool options while more easily extending
arguments on specific regions.
Example which adds '-b 0x10000' only for the COREBOOT CBFS region:
cbfs-files-y += file.bin
file.bin-COREBOOT-cbfstool-opts := -b 0x10000
BUG=None
BRANCH=None
TEST=None
Change-Id: Id9aa461316ae79dd8a7013ee464826925d918e5d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14640
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368519
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Although we have already support for the flash chip N25Q128 there is a
similar type available which has the same geometry and opcodes but
unfortunately a slightly different device type ID. While the already
supported N25Q128 has the ID 0xbb18 this one has the ID 0xba18.
To make both types available in the flash support table, use N25Q128A as
the flash name. This name can be found in the datasheet which can be
found here:
https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf
TEST=Booted and verified that MRC cache could be written
BUG=None
BRANCH=None
Change-Id: Ic8acba7f4c55347e45798ce4bea577094be7e281
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16061
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368518
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the Kconfig value to point to the checklist data files.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Change-Id: I188ad97c96f9259a53393e7959ca24f924bd4fbf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16039
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368517
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We're changing the PWM regulator bounds on Kevin from rev6 onwards, so
we'll need to use different duty cycle values for them. We really want a
proper PWM regulator driver that can calculate these values
automatically from voltages, but until we have that this patch just
hardcodes the new numbers in.
(Yes, this is a patch for the mainboard/google/gru board family that only
touches a file from the rockchip/rk3399 SoC. That too is something
that'll be fixed up in a later CL.)
BRANCH=None
BUG=chrome-os-partner:54888
TEST=Booted Kevin rev4 (for whatever that's worth...).
Change-Id: I8757cc54f2478d20bb948a1a0a7398b0404a7b1f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368410
Commit-Ready: Dan Shi <dshi@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Add the bootblock_c_entry routine to make it more explicit where the
code transitions from assembler to C.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Change-Id: I8c1f397fcdfee1c244ceaac3794881d4d7fb2182
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368406
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8
(BIOS_SPEW). Use the console log level to choose between the serial
port address and NULL and pass it to FSP for the serial port address.
TEST=Build and run on Galileo Gen2.
BUG=None
BRANCH=None
Change-Id: I26b61715ba158389727dd332e20fe6c80bf23784
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/368404
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build. Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Change-Id: I7f6bb14c5c33f6ee1056623a5f6effc96e819b65
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368403
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.
TEST=Build and run bootblock on Galileo Gen2
BUG=None
BRANCH=None
Change-Id: Icb664d0c0b3d16171aba17cabc2e11b5fe202e61
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368402
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
