The romstage.c is more board related than soc specific, like
setting the pwm regulators, so moving it to mainboard/gru.
BRANCH=none
BUG=chrome-os-partner:54819
TEST=Bootup on kevin board
Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/375398
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some SB700-based systems and ROMs support high speed (33MHz) SPI
access instead of the power-on default 16.5MHz. Add an option
to enable high speed SPI access in the bootblock, and set the
default value to Disabled. This greatly decreases boot time on
SB700-based systems, especiall when a large payload is in use.
On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the
command prompt was accessible within 20 seconds of power on, which
incidentally is faster than the proprietary BIOS on the same machine
could even reach the GRUB bootloader.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Test: Booted KGPE-D16 with Linux payload
Reviewed-on: https://review.coreboot.org/16306
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf
Reviewed-on: https://chromium-review.googlesource.com/376862
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add in the base for ELOG for APL. Some PM events still need to be
added but the basic events are logged here. This enables the
basic functionality of ELOG for Apollolake.
BUG=chrome-os-partner:55473
BRANCH=none
TEST=Verified image boots on Amenia
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15937
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c
Reviewed-on: https://chromium-review.googlesource.com/376861
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Call power management utility function clear_wake_sts
from southbridge_smi_sleep before going to sleep.
This is needed to clear the wake status bits in ACPI
registers GPE0.
BUG=chrome-os-partner:55583
BRANCH=None
TEST=Verified that system goes to sleep on lidclose and
powerd_dbus_suspend command issued from built-in
keyboard.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16299
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I204a59f8a19137d6a192ea2d89939eefcd5d41ce
Reviewed-on: https://chromium-review.googlesource.com/376860
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a power management utility function to
clear wake status bits in ACPI GPE0 registers. We need
to call this function before going to sleep from
common smi handler function.
BUG=chrome-os-partner:55583
BRANCH=None
TEST=Verified that system goes to sleep on lidclose and
powerd_dbus_suspend command issued from built-in
keyboard.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16298
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64
Reviewed-on: https://chromium-review.googlesource.com/376859
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On x86 platforms, google_chromeec_early_init() is used to put the EC
into RO mode when there's a recovery request. This is to avoid training
memory multiple times when the recovery request is through an EC host
event while the EC is running RW code. Under that condition the EC will
be reset (along with the rest of the system) when the kernel verification
happens. This leads to an execessively long recovery path because of the
double reboot performing full memory training each time.
By putting this logic into the verstage program this reduces the
bootblock size on the skylake boards. Additionally, this provides the
the correct logic for all future boards since it's not tied to FSP
nor the mainboard itself. Lastly, this double memory training protection
works only for platforms which verify starting from bootblock. The
platforms which don't start verifying until after romstage need to
have their own calls (such as haswell and baytrail).
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16318
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5
Reviewed-on: https://chromium-review.googlesource.com/376858
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SPI drivers for the various chipsets are not consistent in
their handling of when they are accessible. Coupled with the
unknown ordering of boot_device_init() being called this can
lead to unexpected behavior (probing failures or hangs). Instead
move the act of initializing the SPI flash boot device to when
the various infrastructure requires its usage when it calls
boot_device_rw(). Those platforms utilizing the RW boot device
would need to ensure their SPI drivers are functional and
ready when the call happens.
This further removes any other systems failing to boot as
reported in https://ticket.coreboot.org/issues/67.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16300
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Change-Id: Ib3bddf5e26bf5322f3dd20345eeef6bee40f0f66
Reviewed-on: https://chromium-review.googlesource.com/374983
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The return value check was incorect and checking for failure
in the success path. Fix the return value check so that it
actually checks for success.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16303
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ie7960b89a916dec261015c97c3e0552be56b5b5d
Reviewed-on: https://chromium-review.googlesource.com/374468
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Normally machine-mode code operates completely within physical address
space. When emulating less privileged memory accesses (e.g. when the
hardware doesn't support unaligned read/write), it is useful to access
memory through the MMU (and with virtual addresses); this patch
implements this functionality using the MPRV bit.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16260
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: Ic3b3301f348769faf3ee3ef2a78935dfbcbd15fd
Reviewed-on: https://chromium-review.googlesource.com/374466
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Not all SBI calls are implemented, but it's enough to see a couple dozen
lines of Linux boot output.
It should also be noted that the SBI is still in flux:
https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16119
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4
Reviewed-on: https://chromium-review.googlesource.com/374464
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The timestamp code asserts that the _timestamp region (allocated in
memlayout for pre-RAM stages) is large enough for the assumptions it
makes. This is good, except that we often initialize timestamps
extremely early in the bootblock, even before console output. Debugging
a BUG() that hits before console_init() is no fun.
This patch adds a link-time assertion for the size of the _timestamp
region in memlayout to prevent people from accidentally running into
this issue.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Change-Id: Ibe4301fb89c47fde28e883fd11647d6b62a66fb0
Reviewed-on: https://chromium-review.googlesource.com/374461
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
If the boot device is SPI flash use the common one in the
early stages. While tweaking the config don't auto select
SPI_FLASH as that is handled automatically by the rest of the
build system.
CQ-DEPEND=CL:374981,CL:374980
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16202
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22
Reviewed-on: https://chromium-review.googlesource.com/373364
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The chromium tree is currently using a different config for
Chrome OS than what is being built in coreboot.org. Align those
settings to reflect how skylake Chrome OS boards are actually
shipped to provide proper parity between coreboot.org and chromium.
CQ-DEPEND=CL:374980,CL:37336
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16313
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97
Reviewed-on: https://chromium-review.googlesource.com/374981
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A new Kconfig option, DEBUG_PRINT_PAGE_TABLES, is added to control this
behaviour. It is currently only available on RISC-V, but other
architectures can use it, too, should the need arise.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16015
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I52a863d8bc814ab3ed3a1f141d0a77edc6e4044d
Reviewed-on: https://chromium-review.googlesource.com/374131
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update the config variable that gets set to use DMIC 2 channel blob for
intel/apollolake platforms. This flag is set in mainboard.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/16251
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ic6deb9f08d345cc45351d61a7597bc7075ee20f9
Reviewed-on: https://chromium-review.googlesource.com/374123
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split the main() into a couple of smaller functions in order to more
easily extend the payload.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16248
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I4c2b144e2a28c6f15e360d55c49974675e6a80d2
Reviewed-on: https://chromium-review.googlesource.com/374122
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's necessary to call spi_init() prior to calling spi_flash_probe()
such that the SPI drivers can do any work required prior to performing
SPI transactions. It could be argued that the drivers should handle
such situations, however the SPI API implementations seem to assume the
callers ensured spi_init() was called before any SPI transactions.
This fixes systems that failed to boot introduced by [1]. Issue tracked
in https://ticket.coreboot.org/issues/67.
[1] I2aa75f88409309e3f9b9bd79b52d27c0061139c8
https://review.coreboot.org/16200
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16297
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Change-Id: I2d8d5ac685833521f1efe212b07a4b61ba0d9bc3
Reviewed-on: https://chromium-review.googlesource.com/374121
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Check for the existence of TMPFILE with a .exe extension and if found
rename it with no extension. This allows the program to be run and
removed properly.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/15437
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I26928f9b8bf82d1c07fa456a88d624f7a8838bd3
Reviewed-on: https://chromium-review.googlesource.com/373735
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered
preventing the system from entering sleep state. Fix this by calling
halt only if ENV_SMM is not true.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16259
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I3addc1ea065346fbc5dbec9d1ad49bbd0ae05696
Reviewed-on: https://chromium-review.googlesource.com/373733
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Before reading the data provided by EC to the host, ensure that data
ready flag is set. Otherwise, it could result in reading stale/incorrect
data from the data buffer.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified that lidclose event is read correctly by host on reef.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16258
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0
Reviewed-on: https://chromium-review.googlesource.com/373732
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered
preventing the system from entering sleep state. Fix this by calling
halt only if ENV_SMM is not true.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified lidclose behavior on reef.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16257
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If116c8f4e867543abdc2ff235457c167b5073767
Reviewed-on: https://chromium-review.googlesource.com/373731
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
sts_index is calculated incorrectly because of wrong use of
parenthesis. This lead to wrong bit being checked for EC_SMI_GPI on reef
and lidclose event was missed.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified that lidclose event is seen and handled by SMM in
coreboot on reef.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16256
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I56be4aaf30e2d6712fc597b941206ca59ffaa915
Reviewed-on: https://chromium-review.googlesource.com/373730
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Read FSP produced memory HOB and use it to populate DIMM info.
DIMM 'part_num' info is stored statically based on memory/SKU id.
BUG=chrome-os-partner:55505
BRANCH=None
TEST='dmidecode -t 17' and 'mosys -k memory spd print all'
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16246
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73
Reviewed-on: https://chromium-review.googlesource.com/373728
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
disable ps8640 mipi mcs function to avoid that the normal mipi dsi
signal is recognized as msc cmd.
BUG=chrome-os-partner:56346
BRANCH=none
TEST=build pass elm and show ui
Change-Id: I85b9f1e6677e4bf8ab1e30c2e69445079fff2d18
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/373219
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: jitao shi <jitao.shi@mediatek.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
There's no need to be SPI specific w.r.t. how the flash is
connected. Therefore, use the RW boot device to write the
contents of VBNV. The erasable check was dropped because that
information isn't available. All regions should be aligned
accordingly on the platform for the underlying hardware
implementation. And once the VBNV region fills the erase
will fail.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16206
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I07fdc8613e0b3884e132a2f158ffeabeaa6da6ce
Reviewed-on: https://chromium-review.googlesource.com/373368
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Explicitly provide a RW view of an vboot FMAP region. This is
required for platforms which have separate implementations of
a RO boot device and a RW boot device.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16205
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: If8bf2e1c7ca9bff536fc5c578fe0cf92ccbd2ebc
Reviewed-on: https://chromium-review.googlesource.com/373367
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Explicitly provide a RW view of an FMAP region. This is required
for platforms which have separate implementations of a RO boot
device and a RW boot device.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16203
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibafa3dc534f53a3d90487f3190c0f8a2e82858c2
Reviewed-on: https://chromium-review.googlesource.com/373365
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
add delay before and in polling ps8640 ready for reduce the frequence
of polling
BUG=chrome-os-partner:54897
BRANCH=none
TEST=build pass elm and show ui
Change-Id: I5c725eed8110ff9f545c1142ca28bcff336b6860
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/371718
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: jitao shi <jitao.shi@mediatek.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
If the boot device is SPI flash use the common one in the
early stages. While tweaking the config don't auto select
SPI_FLASH as that is handled automatically by the rest of the
build system.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16201
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: If5e3d06008d5529dd6d7c05d374a81ba172d58fd
Reviewed-on: https://chromium-review.googlesource.com/373363
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
