Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: intel/common: Clear wake status bits before sleep

Browse source 
Call power management utility function clear_wake_sts
from southbridge_smi_sleep before going to sleep.
This is needed to clear the wake status bits in ACPI
registers GPE0.

BUG=chrome-os-partner:55583
BRANCH=None
TEST=Verified that system goes to sleep on lidclose and
     powerd_dbus_suspend command issued from built-in
     keyboard.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16299
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I204a59f8a19137d6a192ea2d89939eefcd5d41ce
Reviewed-on: https://chromium-review.googlesource.com/376860
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2016-08-22 22:05:35 -07:00 • committed by chrome-bot
parent cbedfbffd5
commit 4c6f8f3e37
1 changed files with 3 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/soc/intel/common/smihandler.c
View file

@ -176,7 +176,9 @@ void southbridge_smi_sleep(const struct smm_save_state_ops *save_state_ops)
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
break;
}
/* Clear pending wake status bit to avoid immediate wake */
/* Clear the gpio gpe0 status bits in ACPI registers */
clear_gpi_gpe_sts();
/* Tri-state specific GPIOS to avoid leakage during S3/S5 */