Commit graph

19843 commits

Author SHA1 Message Date
Martin Roth
4a5cc9cb44 UPSTREAM: util/lint: Add check for the signed-off-by line
Gerrit will let you push a patch without a signed-off-by line,
although I believe it can't actually be merged.  Instead of catching
it either manually, or when the patch is attempting to be merged,
catch this in the jenkins builder.

BUG=none
BRANCH=none
TEST=none

Change-Id: I5964d9b029ddbc72e39ca9c9db0def8d9f8d61b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23ceb7d240
Original-Change-Id: I80161befa157266dd4e3209839a06ff398aab6bb
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17941
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/427464
2017-01-13 15:21:48 -08:00
Ricardo Ribalda Delgado
27c3dcb522 UPSTREAM: amd/pi: Make BottomIo position configurable
Some PCI peripherals, such as FPGA accelerators, require a great amount
of memory mapped IO. This patch allows the user to select at build time
the bottom IO to leave enough space for such devices.

We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated.

BUG=none
BRANCH=none
TEST=none

Change-Id: If3289ef28c08a2e18b0095ff2be3091e40f1acfa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a132892de6
Original-Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d
Original-Credit-to: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17980
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/427463
2017-01-13 15:21:45 -08:00
Martin Roth
9f192f2c00 UPSTREAM: Kconfig: Remind users to delete .config when switching boards
Because Kconfig default values *ONLY* get set when they are first
configured, if you switch mainboards with an existing .config,
the values will not be set as expected for the new board.

This seems to confuse most users, so put a warning in a visible
location to let them know.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ib4e35cf71c5777adbd15132ad8c7414aadfe4d27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3e26796c4
Original-Change-Id: Ie6a9c2d139ecd841d654943f14c119ebafd632f2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17939
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/427462
2017-01-13 15:21:43 -08:00
Jeffy Chen
b4b708e29f Cherry-pick: rk3288: rtc-rk808: fix rtc time reading issue
After we set the GET_TIME bit, the rtc time can't be read immediately.  We
should wait up to 31.25 us, about one cycle of 32khz.  Otherwise reading
RTC time will return a old time.

BUG=chrome-os-partner:61078
BRANCH=veyron
TEST=Build and Boot

Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/423272
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>

Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/427522
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-01-12 04:51:10 -08:00
William wu
5ea7660b7b gru: Tuning USB 2.0 PHY0 and PHY1 host-port
The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase
compatibility") bypass ODT to set the max driver strength for
the Type-C otg-port, it works well on otg-port when connected
with USB2.0 devices.

Unfortunately, because the Type-C otg-port and host-port are
consisted in one USB2 PHY, so bypass ODT will have an effect
on both host-port and otg-port. I have tested the host-port
eye-diagram, the result shows that if we bypass ODT, the host-
port eye-diagram height will become to high, more than 500mv,
this may cause USB 2.0 high-speed enumeration failure.

This patch bypass ODT for host-port separately, and then we
can reduce the host-port driver strength without affecting
the otg-port driver strength.

BRANCH=gru
BUG=chrome-os-partner:60727
TEST=Boot system, run 'lsusb' command and check if the usb camera
and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are
on usb 1.1 hub, the issue happens. If not, try to run camera app
and then close camera app, repeat until find that the usb camera
is on the usb 1.1 hub.

Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/425739
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2017-01-10 21:34:34 -08:00
Jeffy Chen
4749fc82fd libpayload: usb: Reset ohci controller when trying to shutdown ohci
Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.

Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.

BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.

Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/426338
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2017-01-09 23:47:32 -08:00
Kan Yan
acea6e2a20 libpayload: Add VPD address into lib_sysinfo
BUG=chrome-os-partner:56947
TEST=Verifed country code can be parsed from VPD in depthcharge.
BRANCH=None

Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc
Signed-off-by: Kan Yan <kyan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/425819
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-09 23:47:22 -08:00
Arthur Heymans
c5942c3879 UPSTREAM: mb/asus/p5gc-mx: Use common/gpio.h
Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to
set up GPIOs", which was not rebased on addition of this board.

Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18047
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425987
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:47:03 -08:00
Patrick Georgi
9782512355 UPSTREAM: libpayload: usb: handle situation with no free device address
Change-Id: I1308bdca90f1a09d980f384ee85552198a39b965
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1260940
Original-Reviewed-on: https://review.coreboot.org/18036
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425986
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:47:00 -08:00
Patrick Georgi
508c02c15a UPSTREAM: libpayload: xhci: plug leak
Change-Id: Ia163872846906c6c78144a984a405812f856f626
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1325835
Original-Reviewed-on: https://review.coreboot.org/18035
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425985
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:58 -08:00
Patrick Georgi
b4e7e4c8eb UPSTREAM: libpayload: timer: cast cpu_khz to make sure 64bit math is used
Change-Id: Iaf84de2330b433076a66c22fa72ffb45e957c0dc
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1261177
Original-Reviewed-on: https://review.coreboot.org/18034
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425984
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:56 -08:00
Patrick Georgi
c1e1da8f10 UPSTREAM: util/romcc: avoid shifting more than the variable's width
That's undefined behavior in C

Change-Id: I671ed8abf02e57a7cc993d1a85354e905f51717d
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1229557
Original-Reviewed-on: https://review.coreboot.org/18014
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425983
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:53 -08:00
Arthur Heymans
4795dcf9f2 UPSTREAM: nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>
Nothing from that header is used or even declared since
CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel
hardware.

Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18044
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425982
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:51 -08:00
Arthur Heymans
58bf6ac2ab UPSTREAM: sb/ich7: Use common/gpio.h to set up GPIOs
This is more consistent with newer Intel targets.

This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.

Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17639
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425981
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:48 -08:00
Philipp Deppenwiese
3289641a40 UPSTREAM: payloads/external/SeaBIOS: Bump version to 1.10.1
Changes since SeaBIOS 1.9.3

Release 1.10.0:
* Initial support for Trusted Platform Module (TPM) version 2.0
* Several USB XHCI timing fixes on real hardware
* Support for "LSI MPT Fusion" scsi controllers on QEMU
* Support for virtio devices mapped above 4GB
* Several bug fixes and code cleanups

Release 1.10.1:
* Updates for QEMU for reproducible builds

Change-Id: I465700307d72fa44b6900b38b332603ea505ed09
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18026
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425980
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:46 -08:00
Aaron Durbin
8b52514cd2 UPSTREAM: arch/x86: fix cmos post logging in non romcc bootblock
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and
that function is reponsible for bootstrapping the cmos post register
contents. Without this function being called none of the cmos post
functionality works correctly. Therefore, add a call to lib/bootblock.c
which the C_ENVIRONMENT_BOOTBLOCK SoCs use.

BUG=chrome-os-partner:61546

Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18043
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425979
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:44 -08:00
Timothy Pearson
241ab541b0 UPSTREAM: src/amd: Add common definition of AMD ACPI MMIO address
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.

Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18032
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425978
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-09 23:46:41 -08:00
Arthur Heymans
4c2258fe29 UPSTREAM: mb/ga-m57sli-s4: Fix early uart output
The console output is garbled until it is fixed in ramstage
by devicetree which sets the uart clock predivider correctly.

Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17969
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425495
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-01-06 20:39:39 -08:00
Matt DeVillier
8e0c60d818 UPSTREAM: google/auron: Fix omitted ACPI KB backlight for variants
Restores KB backlight functionality for auron variants
gandof, lulu, and samus.

TEST: boot Lulu and observe KB backlight functional

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17960
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4
Reviewed-on: https://chromium-review.googlesource.com/425293
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 18:40:49 -08:00
Matt DeVillier
691d33303a UPSTREAM: Add/Combine Broadwell Chromebooks using variant board scheme
Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.

Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]

Additionally, some minor cleanup/changes were made:
 - I2C devices set to use level (vs edge) interrupt triggering
 - HDA verb entries use simplified macro entry format
 - correct FADT table header version
 - remove unused ACPI device entries / .asl file(s)
 - clean up ACPI code (e.g., trackpad on Lulu)
 - adjust _CID for trackpad on Lulu in order to not load non-functional
    Windows driver (does not affect Linux)
 - remove unused header includes (multiple/various)
 - correct I2C addresses used for SMBIOS device entries
 - correct misc typos etc

The existing auron_paine samus boards are removed.

Variant setup modeled after google/slippy

CQ-DEPEND=CL:425436
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Reviewed-on: https://chromium-review.googlesource.com/424869
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 13:43:22 -08:00
Martin Roth
ca15229e16 UPSTREAM: util/crossgcc: update jenkins-build-toolchain
This allows the make jenkins-build-toolchain to use the
BUILDGCC_OPTIONS variable.  Previously, the options were hardcoded.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17766
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: I5f4c1d3fc8c714ec3640356ae3c86ae157f486d2
Reviewed-on: https://chromium-review.googlesource.com/425295
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:48 -08:00
Nico Huber
f69d14a570 UPSTREAM: buildgcc: Remove quotes around a $CC call
If we use ccache we have to interpret spaces in $CC as separation
characters. The downside is that we can't support spaces in the
compiler's path. But, well...

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18018
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

Change-Id: I4e6e6324389354669a755f570083a40ff00b1bbf
Reviewed-on: https://chromium-review.googlesource.com/425294
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:45 -08:00
Lee Leahy
602985ee3d UPSTREAM: vboot: Remove rmu.bin from FW_MAIN_A and FW_MAIN_B
Add rmu.bin to the list of files that exist only in the read-only
section (COREBOOT) of the SPI flash.

TEST=Build and run on Galileo Gen2.

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18031
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I30cbd3fb2ef1848807e4de4c479dc7a561c1faba
Reviewed-on: https://chromium-review.googlesource.com/425292
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:43 -08:00
Damien Zammit
32d1273318 UPSTREAM: amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)

This patch separates the build into separate .o modules
and links them accordingly.

Currently compiles and links all fam10 roms without
breaking other roms.

Both DDR2 and DDR3 have been completed

TESTED on REACTS: passes all boot tests for 2 boards
 ASUS KGPE-D16
 ASUS KFSN4-DRE

Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
 advansus/a785e-i
 asus/m5a88-v
 avalue/eax-785e

A followup patch may be required to fix the above boards.
See FIXME, XXX tags

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>

Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Reviewed-on: https://chromium-review.googlesource.com/425291
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:40 -08:00
Paul Menzel
a6fbe9e6e4 UPSTREAM: intel/i945 boards: Add romstage time stamps
Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.

Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>

Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Reviewed-on: https://chromium-review.googlesource.com/425290
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:37 -08:00
Lee Leahy
b9939e78cb UPSTREAM: soc/intel/quark: Add monotonic timer support
Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the
TSC for the monotonic timer.  Simplify the routine to get the TSC
frequency.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18002
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6
Reviewed-on: https://chromium-review.googlesource.com/425289
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:35 -08:00
Patrick Georgi
d2ff5f7d3b UPSTREAM: util/romcc: remove dead assignments
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: scan-build (clang 3.8)
Reviewed-on: https://review.coreboot.org/18021
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Iab6fe065faeacfca3b41eb5bae1075dcfb1a2b05
Reviewed-on: https://chromium-review.googlesource.com/425288
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:33 -08:00
Patrick Georgi
88a9311bae UPSTREAM: util/romcc: Ensure that bit shift is valid
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1287090
Reviewed-on: https://review.coreboot.org/18020
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Idbe147c1217f793b0360a752383203c658b0bdce
Reviewed-on: https://chromium-review.googlesource.com/425287
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:30 -08:00
Patrick Georgi
707db62c59 UPSTREAM: util/romcc: avoid leaking a type
Only allocate ptr_type when it's actually used.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1129117
Reviewed-on: https://review.coreboot.org/18017
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Iea5f93601a42f02a1866bdff099f63935fdd5b8d
Reviewed-on: https://chromium-review.googlesource.com/425286
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:28 -08:00
Patrick Georgi
a722342286 UPSTREAM: util/romcc: avoid dereferencing NULL pointer
argv is only filled for macro->argc > 0.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1287089
Reviewed-on: https://review.coreboot.org/18016
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I5ff21098384afc823efa14be3d5565507fb2b3b2
Reviewed-on: https://chromium-review.googlesource.com/425285
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:25 -08:00
Patrick Georgi
1cb1fca53b UPSTREAM: util/romcc: free variable after use
closure_type is copied then never used again. Close that leak.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1287073
Reviewed-on: https://review.coreboot.org/18015
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Idd4201f7fc6495fde5ad2e1feb7e499e38986e92
Reviewed-on: https://chromium-review.googlesource.com/425284
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:23 -08:00
Patrick Georgi
ba4c55e34c UPSTREAM: broadcom/bcm5785: don't treat KBC-DATA as COM1
Add a break statement instead.
While there, fix a bunch of typos in comments.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1229645
Reviewed-on: https://review.coreboot.org/18013
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I465c0188d4b46eabf8d17e69fa0fdc6a9c2ad66e
Reviewed-on: https://chromium-review.googlesource.com/425283
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:20 -08:00
Lee Leahy
f4883a27ef UPSTREAM: soc/intel/quark: Add early debugging code
Add Kconfig values and early debugging code to better segment and debug
the early code in bootblock by using the SD LED as an indicator.  Update
the help text for the debug Kconfig values to point to the various
failure locations.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633
Reviewed-on: https://chromium-review.googlesource.com/425282
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:18 -08:00
Lee Leahy
cb446381f8 UPSTREAM: soc/intel/quark: Fix serial port configuration
Fix serial port configuration broken by how PCI configuration space was
referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default
to enabled).

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146
Reviewed-on: https://chromium-review.googlesource.com/425281
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:15 -08:00
Martin Roth
05b346bbc3 UPSTREAM: util/abuild: Don't set XGCCPATH if it's in the environment
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17723
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I0fa231ca3d33300a671810e994c5be54ac10a18b
Reviewed-on: https://chromium-review.googlesource.com/425280
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:13 -08:00
Arthur Heymans
5d07a3b94f UPSTREAM: mb/asus/p5gc-mx: Remove extra BSEL strap check
This extra check is based on comparing CPU BSEL pins and reports in
MCH configuration. This gives false positives in the case of 1333MHz
CPUs which automatically get downgraded to 1067MHz by the northbridge
(max supported frequency by 945gc).

TESTED with Intel Xeon 5460 (does not boot but completes raminit)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17997
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
Reviewed-on: https://chromium-review.googlesource.com/425279
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:11 -08:00
Arthur Heymans
c888fcfbf6 UPSTREAM: mb/intel/d945gclf: Fix resume from S3 suspend
Checking for dram self refresh in MCHBAR8(SLFRCS) generates false positives.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17996
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I25afd565cae0269616e38ecbcdf385281bae5d1f
Reviewed-on: https://chromium-review.googlesource.com/425278
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:08 -08:00
Arthur Heymans
cc393085fb UPSTREAM: util/inteltool: Add ICH6-10 to BIOS_CNTL list
Without this change inteltool cannot read BIOS_CNTL values nor can it
read the SPIBAR values.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2
Reviewed-on: https://chromium-review.googlesource.com/425277
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:06 -08:00
Arthur Heymans
dff619441a UPSTREAM: util/inteltool: Fix ICH SPIBAR registers
The ICH7 SPIBAR offset and registers are different from later
generation.
ICH8 has a different offset from later generation.
ICH6 has no SPI controller.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I7691bce619089b15805114047bcb1fd121a5722b
Reviewed-on: https://chromium-review.googlesource.com/425276
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:04 -08:00
Arthur Heymans
3a66c90b85 UPSTREAM: sb/nvidia/mcp55: Fix P_state generation
amd_generate_powernow is never called by in lpc_slave_ops.
Move it to lpc_ops like on all other AMD southbridges.

TESTED on Gigabyte ga-m57sli-s4

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I7db036e681d591a19e15dd3eaafb88b72a41bea1
Reviewed-on: https://chromium-review.googlesource.com/425275
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:01:01 -08:00
Arthur Heymans
65263bca42 UPSTREAM: mb/ga-m57sli: Add cmos.default
If the cmos checksum is incorrect it should fall back to sane defaults.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17968
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132
Reviewed-on: https://chromium-review.googlesource.com/425274
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:59 -08:00
Arthur Heymans
8e5d02d266 UPSTREAM: superiotool: Add support for HWM registers on W83627EHG
Based on datasheet: "W83627EHF/EF W83627EHG/EG WINBOND LPC I/O,
Revision : 1.0"

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17457
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia2e5ab8bc454a34a89fe2cf06bfba55261109785
Reviewed-on: https://chromium-review.googlesource.com/425273
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:56 -08:00
Arthur Heymans
a27b4f24cc UPSTREAM: superiotool: Add support for HWM registers on W83627DHG
Based on datasheet: "W83627DHG WINBOND LPC I/O, Version: 1.4"

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17964
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Id20dff7539d926ef6f68265efbfc7420539d9bca
Reviewed-on: https://chromium-review.googlesource.com/425272
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:54 -08:00
Wisley Chen
86f3767774 UPSTREAM: google/snappy: Update DPTF settings
1. Update DPTF TSR1/TSR2 passive/critial trigger points.
   TSR1 passive point:53, critial point:80
   TSR2 passive point:90, critial point:100

2. Update PL1 Min to 4W and PL1 Max to 12W

3. Update thermal relationship table (TRT) setting.

BUG=none
BRANCH=master
TEST=build, boot on snappy dut and verified by thermal team member.

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17955
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023
Reviewed-on: https://chromium-review.googlesource.com/425271
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:52 -08:00
Tim Chen
37987191b7 UPSTREAM: mainboard/google/reef: Update DPTF parameters EVT1_v0.3
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT1_v0.3_20161227.xlsx)

1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
   CPU  critical point:103
   TSR1 passive point:45
   TSR2 passive point:55, critical point:90

2. Change thermal relationship table (TRT) setting.
   Change CPU Throttle Effect on CPU sample rate to 3secs
   Change Charger Effect on Temp Sensor 2 sample rate to 60secs
   Change CPU Effect on Temp Sensor 1 sample rate to 8secs

BUG=chrome-os-partner:60038
BRANCH=master
TEST=build and boot on electro dut

Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17975
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c
Reviewed-on: https://chromium-review.googlesource.com/425270
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:49 -08:00
Patrick Rudolph
a485af6a82 UPSTREAM: sb/intel/common/gpio: Support ICH9M and prior
Write gpio level twice to make sure the level is set
after pins have been configred as GPIO and to minimize
glitches on newer hardware.

Required to set correct GPIO layout on T500.

Tested on T500.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18012
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)

Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41
Reviewed-on: https://chromium-review.googlesource.com/425269
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:47 -08:00
Patrick Georgi
04f16d5a2e UPSTREAM: util/cbfstool: Don't print region information on stderr by default
It's usually not too interesting, so hide it behind -v.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17899
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Icffb5ea4d70300ab06dfa0c9134d265433260368
Reviewed-on: https://chromium-review.googlesource.com/425268
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:44 -08:00
Martin Roth
7821d0697b UPSTREAM: drivers/uart/oxpcie_early.c: remove uart_fill_lb()
uart_fill_lb() was added to drivers/uart/uart8250mem.c, so when the
Oxford OXPCIe952 Kconfig option is enabled, we were getting an error.
"multiple definition of `uart_fill_lb'"

The new version of uart_fill_lb sets the regwidth depending on the
Kconfig symbol DRIVERS_UART_8250MEM_32, so if that's selected, don't
give DRIVERS_UART_OXPCIE as a choice.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ife24ab390553b10b2266809595c2e06463de708c
Reviewed-on: https://chromium-review.googlesource.com/425267
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:42 -08:00
Jonathan Neuschäfer
d2778bb400 UPSTREAM: Kconfig: Document what ASPM means
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17973
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I57dd933ad70ffac95388d832bd5047f2225688e3
Reviewed-on: https://chromium-review.googlesource.com/425266
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:40 -08:00
Jonathan Neuschäfer
f63d01771d UPSTREAM: payloads/external: Download FILO over HTTPS
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17972
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I1b44e32505b96978849d39764ff399a502fa6e84
Reviewed-on: https://chromium-review.googlesource.com/425265
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:37 -08:00