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UPSTREAM: mb/asus/p5gc-mx: Remove extra BSEL strap check

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This extra check is based on comparing CPU BSEL pins and reports in
MCH configuration. This gives false positives in the case of 1333MHz
CPUs which automatically get downgraded to 1067MHz by the northbridge
(max supported frequency by 945gc).

TESTED with Intel Xeon 5460 (does not boot but completes raminit)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17997
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
Reviewed-on: https://chromium-review.googlesource.com/425279
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Arthur Heymans 2016-12-30 18:52:53 +01:00 • committed by chrome-bot
parent c888fcfbf6
commit 5d07a3b94f
1 changed files with 1 additions and 6 deletions
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7
src/mainboard/asus/p5gc-mx/romstage.c
View file

@ -242,12 +242,7 @@ void mainboard_romstage_entry(unsigned long bist)
i945_early_initialization();
m_bsel = MCHBAR32(CLKCFG) & 7;
printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel);
if (c_bsel != m_bsel) { /* Should not happen */
printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n");
outb(0xe, 0xcf9);
halt();
}
printk(BIOS_DEBUG, "CPU BSEL: 0x%x\nMCH BSEL: 0x%x\n", c_bsel, m_bsel);
s3resume = southbridge_detect_s3_resume();