Commit graph

18180 commits

Author SHA1 Message Date
Furquan Shaikh
44d10230b9 UPSTREAM: chromeos: Clean up elog handling
1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.

2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.

3. Remove calls to elog add boot reason and watchdog reset from
mainboards.

BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Reviewed-on: https://chromium-review.googlesource.com/364021
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:42 -07:00
Furquan Shaikh
8bcef6216a UPSTREAM: google/urara: Provide dummy implementations of rec/dev functions
This is required to enable elog support in ChromeOS by default.

BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d
Reviewed-on: https://chromium-review.googlesource.com/364020
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:40 -07:00
Furquan Shaikh
df24f6b203 UPSTREAM: qualcomm/gale: Add required files to enable elog in ramstage
BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15895
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec
Reviewed-on: https://chromium-review.googlesource.com/364019
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:37 -07:00
Furquan Shaikh
e1c2142ca9 UPSTREAM: qualcomm/storm: Add required files to enable elog in ramstage
BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431
Reviewed-on: https://chromium-review.googlesource.com/364018
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:35 -07:00
Furquan Shaikh
5286f625fd UPSTREAM: i2c/ww_ring: Add ww_ring files to ramstage
These files are required by storm and gale boards for enabling elog
support in ramstage.

BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I2bbfee2acf2bfe2f896a8619b1276dcea1b87f16
Reviewed-on: https://chromium-review.googlesource.com/364017
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:33 -07:00
Furquan Shaikh
7e99cef754 UPSTREAM: google/chromeos: Use vboot bootmode functions for elog add boot reason
BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I3ac2b256862758bb5c9e6c2f1311972af474e8f6
Reviewed-on: https://chromium-review.googlesource.com/364016
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:30 -07:00
Furquan Shaikh
661a6b476b UPSTREAM: bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.

BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Reviewed-on: https://chromium-review.googlesource.com/364015
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:28 -07:00
Furquan Shaikh
c1f7925f01 UPSTREAM: vboot: Separate vboot from chromeos
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.

CQ-DEPEND=CL:363941,CL:363940
BUG=chrome-os-partner:55639
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Reviewed-on: https://chromium-review.googlesource.com/364014
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:25 -07:00
Furquan Shaikh
c73f684956 UPSTREAM: drivers/intel/fsp2_0: Update MRC cache with dead version in recovery
If the system is in recovery, store the newly generated MRC data using a
dummy version which is not legit. This ensures that on next normal boot,
new MRC data will be generated and stored.

BUG=chrome-os-partner:55699
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15828
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ib13e8c978dc1b4fc8817fab16d0e606f210f2586
Reviewed-on: https://chromium-review.googlesource.com/364013
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:23 -07:00
Furquan Shaikh
518aa30982 UPSTREAM: soc/intel/common: Store MRC data in next available slot in the cache
Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.

BUG=chrome-os-partner:55699
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Reviewed-on: https://chromium-review.googlesource.com/364012
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:21 -07:00
Aaron Durbin
c5daf3456e UPSTREAM: mainboard/google/slippy: remove unobtainable mainboard
The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Reviewed-on: https://chromium-review.googlesource.com/364011
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:18 -07:00
Aaron Durbin
79bdc204e3 UPSTREAM: mainboard/google/bolt: remove unobtainable mainboard
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Reviewed-on: https://chromium-review.googlesource.com/364010
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:16 -07:00
Bora Guvendik
81f842a048 UPSTREAM: soc/intel/apollolake: Disable monitor mwait
The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around

BUG=chrome-os-partner:55110
BRANCH=None
TEST=None

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Reviewed-on: https://chromium-review.googlesource.com/363939
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:13 -07:00
Paul Kocialkowski
35f905285b UPSTREAM: Rename VB_SOURCE to VBOOT_SOURCE for increased clarity
This renames the VB_SOURCE variable to VBOOT_SOURCE in the build system,
providing increased clarity about what it represents.

Since the submodule itself is called "vboot", it makes sense to use that
name in full instead of a very shortened (and confusing) version of it.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15824
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: Ib343b6642363665ec1205134832498a59b7c4a26
Reviewed-on: https://chromium-review.googlesource.com/363938
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:11 -07:00
Paul Kocialkowski
8d3ca5e0ba UPSTREAM: chromeec: Use CHROMEEC_SOURCE with fallback instead of hardcoding path
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS
EC source path, with a fallback to 3rdparty/chromeec.

This allows specifying an external path for the CrOS EC source path.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146
Reviewed-on: https://chromium-review.googlesource.com/363937
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:09 -07:00
Lee Leahy
3071039fd7 UPSTREAM: arch/x86: Add bootblock and postcar support for SOC MTRR access
Quark does not support the rdmsr and wrmsr instructions.  Use SOC
specific routines to configure the MTRRs on Quark based platforms.
Add cpu_common.c as a build dependency to provide access to the routine
cpu_phys_address_size.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15846
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19
Reviewed-on: https://chromium-review.googlesource.com/363936
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:06 -07:00
Lee Leahy
abc216822d UPSTREAM: cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Reviewed-on: https://chromium-review.googlesource.com/363935
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:04 -07:00
Damien Zammit
fe4cabadaf UPSTREAM: nb/intel/x4x: Fix CAS latency detection and max memory detection
Now hardcode maximum memory frequency capability to 800MHz, as
all chipsets in x4x family support PC2-6400 according to the datasheet.
CAS latency detection also relies on this, and has been cleaned up.

Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination,
so disable this combination for now, and reduce to 667MHz instead.
Still don't know why this is the case, but FSB1333/667 works.

These changes should now allow existing configurations to continue working,
while providing support for previously unworking configurations, due to
previous buggy CAS latency detection code.

TESTED: on GA-G41M-ES2L
CPU: E5200 @ 2.50GHz (FSB 800MHz)

2x 1GB 667MHz hynix	worked @ 667
1x 2GB 800Mhz ARAM	worked @ 800
1x 1GB 667Mhz StarRam	worked @ 667
2x 2GB 800Mhz (generic)	worked @ 800

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15818
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>

Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
Reviewed-on: https://chromium-review.googlesource.com/363934
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:02 -07:00
Aaron Durbin
00e49c22aa UPSTREAM: device: include devicetree in bootblock stage
Allow bootblock to get access to the static device tree like
other early stages. device_romstage.c was renamed to
device_simple.c to better articulate the usage since it's not
just being used in romstage.

BUG=chrome-os-partner:55357
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins)

Change-Id: I3d63d2754c737cc738c09a3e3b3b468362fb78d1
Reviewed-on: https://chromium-review.googlesource.com/363933
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:55:59 -07:00
Aaron Durbin
6c36bab99b UPSTREAM: soc/nvidia/tegra124: remove cache_policiy option
All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>

Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Reviewed-on: https://chromium-review.googlesource.com/363932
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:55:57 -07:00
Lee Leahy
40716f66ab UPSTREAM: drivers/intel/fsp2_0/header_util: Convert UPD headers
Convert the FSP 2.0 UPD headers from typedef to struct:
* FSP_UPD_HEADER
* FSPM_ARCH_UPD

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15856
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iab241ea07c955e95ff988a4a30103d2a112179b6
Reviewed-on: https://chromium-review.googlesource.com/363931
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:55:55 -07:00
Lee Leahy
a6b43fa16a UPSTREAM: arch/x86: Generate a map file for the postcar stage
Place a map file for the postcar stage and place it into
build/cbfs/fallback.

TEST=Build and run on Galileo Gen2

Change-Id: I349c06e3c610db5b3f2511083208db27110c34d0
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15845
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363390
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 15:16:44 -07:00
Lee Leahy
661548dbc5 UPSTREAM: arch/x86: Organize ramstage to match other stages
Move the ramstage files to the beginning of the section. Eliminate
duplicate conditionals.

TEST=Build and run on Galileo Gen2

Change-Id: I461a5b78a76bd0d2643b85973fd0a70bc5e89581
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15892
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363389
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 15:16:42 -07:00
Lee Leahy
e1e3d89a4d UPSTREAM: arch/x86: Move romstage files into romstage section
Move the romstage files into the romstage section of the file.
Eliminate duplicate conditional statements.

TEST=None

Change-Id: Ie2d65cef3797a2c091c0cd76b147b30a765332ad
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15891
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363388
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 15:16:40 -07:00
Lee Leahy
98d85e8789 UPSTREAM: arch/x86: Move postcar stage commands into place
Move the postcar commands to in between romstage and ramstage. Add the
stage header.

TEST=Build and run on Galileo Gen2

Change-Id: I530da6afd8ccbcea217995ddd27066df6d45de22
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15844
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363387
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 15:16:37 -07:00
Aaron Durbin
6083c0b340 UPSTREAM: drivers/elog: put back 4KiB limit
The removal of ELOG_FLASH_BASE and ELOG_FLASH_SIZE resulted
in the FMAP region for the eventlog to be honored. However,
certain systems seem to have a large eventlog region that
wasn't being used in practice. Because of the malloc() in the
eventlog init sequence a large allocation was now being requested
that can exhaust the heap. Put back the 4KiB capacity until
the resource usage is fixed.

BUG=chrome-os-partner:55593

Change-Id: Ib54b396b48e5be80f737fc3feb0d58348c0d2844
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15835
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363386
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 15:16:35 -07:00
Kyösti Mälkki
4ec9505dc0 UPSTREAM: intel car: Use MTRR WRPROT type for XIP cache
XIP cachelines contain the executable to run, we never want
that to get modified. With the change such erronous writes
are ignored and next cacheline miss will fetch from boot
media (SPI / FWH flash).

Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15778
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363385
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 12:27:12 -07:00
Kyösti Mälkki
08bf481667 UPSTREAM: intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.

Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15761
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363384
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 12:27:09 -07:00
Lee Leahy
b1aef9ad50 UPSTREAM: lib: Don't require ULZMA compression for postcar
The build fails during postcar when ULZMA compression is not selected.
Fix cbfs.c to support LZ compression for ramstage as well.

The build error is:
build/postcar/lib/cbfs.o: In function `cbfs_load_and_decompress':
/home/lee/coreboot/public/src/lib/cbfs.c:116: undefined reference to
`ulzman'
make: *** [build/cbfs/fallback/postcar.debug] Error 1

TEST=Build and run on Galileo Gen2

Change-Id: I7fa8ff33c0d32e0c5ff5de7918e13e6efb1df38e
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15841
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363383
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 12:27:07 -07:00
Lee Leahy
5f83e13ec3 UPSTREAM: drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-M
Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
Quark executes romstage directly from the SPI flash part (in-place),
but loads FSP-M into ESRAM. This split occurs because ESRAM is too
small to hold everything while debugging.

Platforms executing FSP-M directly from the SPI flash need to select
FSP_M_XIP.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15848
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363382
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 12:27:05 -07:00
Lee Leahy
1f66befad4 UPSTREAM: src/lib: Enable display of cbmem during romstage and postcar
Enable the display of cbmem during romstage and postcar. Add a Kconfig
value to prevent coreboot images from increasing in size when this
feature is not in use.

TEST=Build and run on Galileo Gen2

Change-Id: Ib70ad517ebf7d37a7f46ba503b4432c7c04d7ded
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15842
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363381
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 12:27:02 -07:00
Lee Leahy
0b0c9454ee UPSTREAM: drivers/uart: Enable debug serial output during postcar
Build the UART drivers for the postcar stage.

TEST=Build and run on Galileo Gen2

Change-Id: I8bf51135ab7e62fa4bc3e8d45583f2feac56942f
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15843
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363380
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 12:27:00 -07:00
Martin Roth
f326097fda rockchip/rk3399: Halt if we get an invalid odt or drv value
When we were pushing the updated sdram.c to coreboot.org, the compiler
there found that we were not initializing vref_value_dq in all code
possible code paths.

This patch updates those code paths to halt the system.

Branch=none
Bug=none
Test=Built with coreboot.org toolchain and verified that the compile
errors were gone.

Change-Id: I0ad4207dc976236d64b6cdda58d10bcfbe1fde11
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362726
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-25 17:08:57 -07:00
Furquan Shaikh
dfaebc26cf UPSTREAM: intel/skylake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Reviewed-on: https://chromium-review.googlesource.com/362976
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:29 -07:00
Furquan Shaikh
d31f4c44a6 UPSTREAM: intel/apollolake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68
Reviewed-on: https://chromium-review.googlesource.com/362975
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:26 -07:00
Furquan Shaikh
061065b518 UPSTREAM: google/chromeos: Add support for saving recovery reason across reboot
On some x86 platforms (skylake, apollolake), we observe reboots at
different steps during the FSP initialization. These additional reboots
result in loss of recovery request because vboot_reference library
clears recovery request on vbnv once verification is complete and it has
made a decision about which boot path to take(normal/dev, slot-a/slot-b,
recovery).

Provide a way to allow mainboards/chipsets to inform recovery module in
vboot2 to save recovery reason to survive unexpected reboots. The
recovery reason is set in vbnv after vboot_reference library completes
its verification and clears the reason in vbnv while jumping to
payload.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15802
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ie96be9aeb42c8209d8215943409e6327d6a8bf98
Reviewed-on: https://chromium-review.googlesource.com/362974
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:24 -07:00
Furquan Shaikh
73a680307b UPSTREAM: lib/bootmode: Use newly-add recovery module
Use the newly added check recovery request function from recovery module
in vboot2 to check for a pending recovery request.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I354cc094f1e5d0044cf13e5bc28246f058d470c6
Reviewed-on: https://chromium-review.googlesource.com/362973
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:22 -07:00
Furquan Shaikh
2466d61d04 UPSTREAM: google/chromeos: Add recovery module in vboot2
Add recovery module in vboot2 that checks if a recovery request is
pending and returns appropriate reason code:
1. Checks if recovery mode is initiated by EC.
2. Checks if recovery request is present in VBNV.
3. Checks if recovery request is present in handoff for post-cbmem
stages.
4. Checks if vboot verification is complete and looks up selected region
to identify if recovery is requested by vboot library.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I31e332a4d014a185df2434c3730954e08dc27281
Reviewed-on: https://chromium-review.googlesource.com/362972
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:19 -07:00
Furquan Shaikh
57ede7a07d UPSTREAM: vboot: Clean up vboot code
1. Remove unused functions/structures.
2. Add checks for NULL return values.
3. Change prefixes to vb2 instead of vboot for functions used internally
within vboot2/
4. Get rid of vboot_handoff.h file and move the structure definition to
vboot_common.h
5. Rename all functions using handoff structure to have prefix
vboot_handoff_*. All the handoff functions can be run _only_ after cbmem
is online.
6. Organize vboot_common.h content according to different
functionalities.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb
Reviewed-on: https://chromium-review.googlesource.com/362971
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:17 -07:00
Furquan Shaikh
3ab2c34d99 UPSTREAM: skylake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Reviewed-on: https://chromium-review.googlesource.com/362970
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:15 -07:00
Furquan Shaikh
17340e74e7 UPSTREAM: apollolake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Reviewed-on: https://chromium-review.googlesource.com/362879
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:12 -07:00
Furquan Shaikh
31ea962219 UPSTREAM: intel/amenia: Add chromeos.c to verstage
BUG=chrome-os-partner:55431
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15823
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I94fe54c12d7438a71f81a9053cc9785c0aa1e6cf
Reviewed-on: https://chromium-review.googlesource.com/362878
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 15:02:10 -07:00
Subrata Banik
d6a308b3a9 UPSTREAM: Makefile: Add uCode binary to FIT
Currently, on Intel Skylake the uCode binary is added to
CBFS based on the config option CBFS_EXTERNAL_HEADER. But
the entry is missing into the Firmware Interface Table, so
add it there.

BRANCH=none
BUG=chrome-os-partner:55403, chrome-os-partner:53077
TEST=built and verified FIT table has ucode entry.

Change-Id: I7dd7459ff7d2468f0aff66eb3ee9c2e3d7eda501
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15783
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361855
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-24 10:19:40 -07:00
Duncan Laurie
277ef406e5 UPSTREAM: google/reef: Enable PS/2 keyboard driver by default
This device has a built-in keyboard that should be enabled by default
or it will not work in firmware. This was tested to ensure that TAB
(display info) and Ctrl+D (enter developer mode) are functional at the
Chrome OS recovery screen.

BUG=chrome-os-partner:55549

Change-Id: I60156f1fc001b88deac69e03e02e9d8277fbc38d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15782
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362860
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-24 10:19:37 -07:00
Aaron Durbin
518a427d4e UPSTREAM: soc/intel/apollolake: ensure usb port 0 is in host mode
The controller for device mode USB is not plan of record
on apollolake. However, one still needs to configure the
one port to be host mode by default such that the devices
work as expected when plugged into the board.

BUG=chrome-os-partner:54581,chrome-os-partner:54656
TEST=Enabled xdci controller. Used USB type C->A dongle to
check that a mass storage device worked on port 0 on
reef.

Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15781
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362769
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-24 10:19:35 -07:00
Aaron Durbin
45b5115584 UPSTREAM: drivers/elog: remove elog Kconfig variables
Now that FMAP is a first class citizen in coreboot
there's no reason to have alternate locations for ELOG.
If one wants eventlog support they need to specify the
ELOG entry in the FMAP. The one side effect is that
the code was previously limiting the size to 4KiB
because the default ELOG_AREA_SIZE was 4KiB. However,
that's no longer the case as the FMAP region size is
honored.

Change-Id: I4ce5f15032387155d2f56f0de61f2d85271ba606
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15814
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362768
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-24 10:19:33 -07:00
Kyösti Mälkki
f2b7c5bead UPSTREAM: intel/haswell: Remove useless MTRR clear
At this state, variable MTRRs are disabled. We overwrite this MTRR entry
before they are re-enabled.

Change-Id: Ieedf90f65514d848905626e75be496e08f710d91
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15794
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362767
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-24 10:19:30 -07:00
Kyösti Mälkki
8f7ff90f8e UPSTREAM: intel/haswell post-car: Minor fix on MTRR setting
Change-Id: I65f0ad430bdcc2065c1e873743da04201a68d9c9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15796
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362766
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-24 10:19:28 -07:00
Kyösti Mälkki
8dd126e5d6 UPSTREAM: intel/haswell: Add asmlinkage for romstage_after_car()
Change-Id: Ib3c973d2e89d4c25c3bf1e52662fbfcb4b1e4355
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15789
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362765
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-24 10:19:26 -07:00
Aaron Durbin
2e6bf5bf9e UPSTREAM: cpu/x86/mtrr: correct variable MTRR calculation around 1MiB boundary
The fixed MTRRs cover the range [0:1MiB). While calculating the
variable MTRR usage the 1MiB boundary is checked such that
an excessive number of MTRRs aren't used because of unnatural
alignment at the low end of the physical address space. Howevever,
those checks weren't inclusive of the 1MiB boundary. As such a
variable MTRR could be used for a range which is actually covered
by the fixed MTRRs when the end address is equal to 1MiB. Likewise,
if the starting address of the range lands on the 1MiB boundary
then more variable MTRRs are calculated in order to meet natural
alignment requirements.

Before:
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0
0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6
0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0
0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1
0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 7/17.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007ffff00000 type 0
MTRR: 1 base 0x000000007b800000 mask 0x0000007fff800000 type 0
MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
MTRR: 3 base 0x0000000080000000 mask 0x0000007fe0000000 type 0
MTRR: 4 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0
MTRR: 5 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1
MTRR: 6 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0

After:
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0
0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6
0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0
0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1
0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 6/8.
MTRR: WB selected as default type.
MTRR: 0 base 0x000000007b800000 mask 0x0000007fff800000 type 0
MTRR: 1 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
MTRR: 2 base 0x0000000080000000 mask 0x0000007fe0000000 type 0
MTRR: 3 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0
MTRR: 4 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1
MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0

BUG=chrome-os-partner:55504

Change-Id: I7feab38dfe135f5e596c9e67520378a406aa6866
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15780
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362845
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-23 13:05:18 -07:00