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UPSTREAM: intel car: Use MTRR WRPROT type for XIP cache

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XIP cachelines contain the executable to run, we never want
that to get modified. With the change such erronous writes
are ignored and next cacheline miss will fetch from boot
media (SPI / FWH flash).

Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15778
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363385
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-07-21 19:51:01 +03:00 • committed by chrome-bot
parent 08bf481667
commit 4ec9505dc0
2 changed files with 2 additions and 2 deletions
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2
src/cpu/intel/car/cache_as_ram_ht.inc
View file

@ -310,7 +310,7 @@ no_msr_11e:
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx

2
src/cpu/intel/model_6ex/cache_as_ram.inc
View file

@ -111,7 +111,7 @@ clear_mtrrs:
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx