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UPSTREAM: intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE

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Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.

Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15761
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363384
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-07-20 10:49:38 +03:00 • committed by chrome-bot
parent b1aef9ad50
commit 08bf481667
2 changed files with 32 additions and 11 deletions
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11
src/cpu/intel/model_206ax/cache_as_ram.inc
View file

@ -20,7 +20,11 @@
#include <arch/acpi.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
* and the space used by the reference code. These 2 values combined should
* be a power of 2 because the MTRR setup assumes that. */
#define CACHE_AS_RAM_SIZE \
(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
/* Cache 4GB - MRC_SIZE_KB for MRC */
@ -159,9 +163,8 @@ clear_mtrrs:
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
/* Set up the stack pointer below MRC variable space. */
movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
/* Restore the BIST result. */

32
src/northbridge/intel/sandybridge/Kconfig
View file

@ -69,18 +69,35 @@ config MRC_CACHE_SIZE
depends on !CHROMEOS
default 0x10000
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/sandybridge/bootblock.c"
if USE_NATIVE_RAMINIT
config DCACHE_RAM_BASE
hex
default 0xff7e0000 if !USE_NATIVE_RAMINIT
default 0xfefe0000 if USE_NATIVE_RAMINIT
default 0xfefe0000
config DCACHE_RAM_SIZE
hex
default 0x20000
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/sandybridge/bootblock.c"
config DCACHE_RAM_MRC_VAR_SIZE
hex
default 0x0
endif # USE_NATIVE_RAMINIT
if !USE_NATIVE_RAMINIT
config DCACHE_RAM_BASE
hex
default 0xff7e0000
config DCACHE_RAM_SIZE
hex
default 0x1c000
config DCACHE_RAM_MRC_VAR_SIZE
hex
@ -88,7 +105,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
config MRC_FILE
string "Intel System Agent path and filename"
depends on !USE_NATIVE_RAMINIT
default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help
The path and filename of the file to use as System Agent
@ -96,6 +112,8 @@ config MRC_FILE
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000 if !USE_NATIVE_RAMINIT
default 0xf0000000
endif # !USE_NATIVE_RAMINIT
endif