I did change the /bin/bash to /bin/sh per the comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@919 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Read port for early serial console from Kconfig
* Change naming from SP (serial port) to COM to be consistent with
Kconfig
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@917 f3766cd6-281f-0410-b1cd-43a5c92072e9
This required lots of preparatory work to not make the existing stage0
situation worse.
Thanks to Jason Zhao we got a skeleton CAR code for VIA C7 based on
older v2 code.
I cleaned it up, modified it to fit into the improved v3 stage0 code
infrastructure and believe this is mostly merge-ready.
Thanks to Bari Ari for getting the code to me for rewrite/review.
Thanks to Corey Osgood who kept me going with helpful early tests and
motivation.
Thanks to everybody who reviewed my code.
CONFIG_CARTEST shall not be enabled (breaks the build).
CONFIG_XIP_ROM_{SIZE,BASE} shall not be set (breaks the build).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@915 f3766cd6-281f-0410-b1cd-43a5c92072e9
affected. This mostly targets pci_*_config*() calls.
This is part of my quest to make existing code more readable without
looking up the meaning of magic numbers.
Ron pointed out that this enables better kscope usage.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@913 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@912 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@911 f3766cd6-281f-0410-b1cd-43a5c92072e9
up correctly on bus 1 --- i.e., the scan of the 8111 bridge works. It
even
tries to find the vga rom to run it, which we did not get before.
the pci bus map built by coreboot matches simnow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@910 f3766cd6-281f-0410-b1cd-43a5c92072e9
We had a jump instead of a call to stage1_main in geodelx/stage0.S. That
means all accesses to bist and init_detected were off by 8 bytes and
collided with accesses to the global variable pointer.
Found during my cleanup runs.
This bug had the following effects:
1.) If gcc had decided to reload bist from stack after initializing the
global variable pointer, bist would have been nonzero, an indicator for
processor failure.
2.) If gcc had decided to use the stack location of bist as a scratch
register (and it probably is free to do so as long as the contents are
restored before returning), it would have clobbered the global variable
pointer, leading to NULL pointer dereferences.
3.) Any accesses to init_detected would have resulted in accessing 4
bytes above the top of stack (0x87ffc-0x87fff), something the rest of
the code deliberately avoids.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@909 f3766cd6-281f-0410-b1cd-43a5c92072e9
implementations. Factor out the 16 bit code with associated protected
mode activation.
I'm open to moving even more common code out, but this is a well-defined
start.
This cleanup has been prepared for by r902, r905 and r907.
Boot tested on qemu. Build tested on i586, geodelx, k8.
The diffstat is most enlightening:
amd/stage0.S | 145 ---------------------------------------------
geodelx/stage0.S | 145 ---------------------------------------------
i586/stage0.S | 145 ---------------------------------------------
stage0_common.S | 145 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 148 insertions(+), 432 deletions(-)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@908 f3766cd6-281f-0410-b1cd-43a5c92072e9
CAR code.
Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order.
Now we can split out the common parts more easily and concentrate on the
differences.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@907 f3766cd6-281f-0410-b1cd-43a5c92072e9
Quick fix to Rules.make to avert issues with half-created statictree.[ch]
causing compiles to fail. This was confusing for users.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@906 f3766cd6-281f-0410-b1cd-43a5c92072e9
except for the actual CAR code and inital #includes and #defines.
Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order to the best variant
present in the 3 files.
Now we can split out the common parts more easily and concentrate on the
differences.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@905 f3766cd6-281f-0410-b1cd-43a5c92072e9
a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
This makes SimNow work, since apparently though the codec is
present in Simnow, it is non functional.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@904 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@903 f3766cd6-281f-0410-b1cd-43a5c92072e9
byte-for-byte identical. That makes factoring out easier.
Fix a duplicated BIST save for K8.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@902 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@901 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@900 f3766cd6-281f-0410-b1cd-43a5c92072e9
arch/x86/i586/stage0.S to make it consistent with the other variants of
that code.
Clean up two superfluous rules from arch/x86/Makefile which were needed
before. That makefile change also fixes a latent bug which may have been
exposed by later additions to the tree.
Compile tested on all arches.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@899 f3766cd6-281f-0410-b1cd-43a5c92072e9
amd/Kconfig. Fix serengeti Makefile.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@898 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@897 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@896 f3766cd6-281f-0410-b1cd-43a5c92072e9
m57sli) add incoherent ht chain support to stage1 as well.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@895 f3766cd6-281f-0410-b1cd-43a5c92072e9
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@894 f3766cd6-281f-0410-b1cd-43a5c92072e9
23K, too large.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@893 f3766cd6-281f-0410-b1cd-43a5c92072e9
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@892 f3766cd6-281f-0410-b1cd-43a5c92072e9
obsolete chip.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@891 f3766cd6-281f-0410-b1cd-43a5c92072e9
awful chip. But it builds.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@890 f3766cd6-281f-0410-b1cd-43a5c92072e9
version, with these typos, compiled.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@889 f3766cd6-281f-0410-b1cd-43a5c92072e9
dts and making the ops struct non-static.
This is the second pass on this patch, I have put the changes in that
Uwe requested, I hope I got them all. I have not heard back from Uwe yet
but this patch is urgent.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@888 f3766cd6-281f-0410-b1cd-43a5c92072e9
There are some interesting issues here. The enables for the various
devices are a global bitmask:
Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
But v3 would allow us to not have the bit mask. OTOH, we would end up
with 3 .dts files for the pcie ports for this enable; good or bad?
GOOD --> highly custom configuration possible for each port
BAD --> 3 .dts files
Part of the issue is that the link from the dts to the device operations
structure is done as follows:
struct device_operations sb600_usb2 = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB600_USB2}}},
And this structure is named in the .dts for that device_operations:
{
device_operations = "sb600_usb2";
};
requiring a different dts node for each set of device_operations.
The device tree compiler generates the code to create these connections
and puts that code into the the static_tree.c file.
Having a .dts file for each port gives us a lot of flexibility; but is
it too inconvenient? This is an unresolved problem; unhandled at present
for the *6* USB ports for the sb600.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@886 f3766cd6-281f-0410-b1cd-43a5c92072e9
My apologies.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@881 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnch@gmail.com>
Acked-by: Ronald G. Minnich <rminnch@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@880 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Coding style and whitespace fixes.
- Remove obsolete comments, fix incorrect ones.
- Use the full/canonical name of mainboards/vendors everywhere.
- Update the list of USB Debug capable chipsets from
http://www.coreboot.org/EHCI_Debug_Port.
- s/LB/CB/ for the CONSOLE_PREFIX kconfig option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
We need to figure out if we should just grow stage0. My inclination is
to say 'yes'.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard that we learned with the serengeti that we needed. New
function in pnp that is for reading. new prototype in pnp.h. New
constants for ite8716f.
This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow.
Now that we have two boards under way we can hopefully see our way to
getting more put in. The 690 is the obvious next choice.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@876 f3766cd6-281f-0410-b1cd-43a5c92072e9
with buildrom. Informally acked by Ron.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@875 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@874 f3766cd6-281f-0410-b1cd-43a5c92072e9
such as .note.this.that. These new note names were making builds
unbuildable on (e.g.) fc9.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@873 f3766cd6-281f-0410-b1cd-43a5c92072e9
moved to stage1 ROM code. Make the struct for nodeid/coreid generic to
x86. Create the functions for existing architectures are a model for
future architectures (VIA coming soon we hope).
Move includes so that things build correctly now.
This is actually a small patch that impacted a number of files due to
include order changes. This is build and boot tested on simnow and
build tested on geode.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@872 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@871 f3766cd6-281f-0410-b1cd-43a5c92072e9
