BUG=none
BRANCH=none
TEST=none
Change-Id: I7488d471b8e4c4a5fb8ea79302a1b39eee1e3333
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bddf86a259
Original-Change-Id: I5fcc83328441ccfb34ee63a7406d26e393633c21
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19685
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/506198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
There is code to adjust the mapping down if a mmap fails
at a physical address. However, if the address is less
than the page size of the system then the physical offset will
underflow. This can actually cause a kernel panic on when
operating on /dev/mem.
The failing condition happens when the requested mapping at 0
fails in the kernel. The fallback path is taken and page size
is subtracted from 0 making a very large offset. The PAT code
in the kernel fails with a BUG_ON in reserve_memtype() checking
start >= end. The kernel needs to be fixed as well, but this
fallback path is wrong as well.
BUG=b:38211793
Change-Id: Idd5b22027633e5e1febd140336244f25a5304de4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7ad44eed08
Original-Change-Id: I32b0c15b2f1aa43fc57656d5d2d5f0e4e90e94ef
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19679
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506197
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Id63191e6f235622c0a93addf8a1afe97bb68bf78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a7092750b2
Original-Change-Id: I2fa1548ba1906db80ce3119eec58de9629f91ed7
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19296
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506224
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I01428c56e7e416f191c07278e1241ef43e7a5d9f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2a59a44416
Original-Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/13749
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506223
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
And don't link it. It's for ROMCC.
To make code happy that uses the ROMCC interface read_option(),
read_option_lowlevel() is ported to mc146818rtc.c along with
a message to use get_option() instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9e6b1aeca2824199bbdec7dcb2bee9306d0e46cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c3da3fe1d3
Original-Change-Id: I54ea08de034766c8140b320075d36d5e811582fa
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19663
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506221
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieae7f68cadd2f41d94979c67267620272ed91319
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7d46e96ed7
Original-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18993
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506220
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: If91dd643c754fd049952065dba56bab731b7f449
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cfd433b96d
Original-Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19680
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506219
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This board features a PATA port.
TESTED PATA drive works in SeaBIOS and OS.
BUG=none
BRANCH=none
TEST=none
Change-Id: I139e711a715782032c8eecb7f983aecd991c15b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd2e35edc1
Original-Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19627
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506218
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: I65b001b851b9cec3cf6cbbc0d345127f57912dd8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 55cad16ca5
Original-Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/506217
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: Ic527b2b23ea9cbaf42bd9411af766db9c053f13d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 48dbc663d7
Original-Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19672
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506215
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Delay for a while after the switch operations to let the card recover.
TEST=Build and run on Galileo Gen2
Change-Id: I5164215678ef54a0d3101b1f92efffe0ef26f375
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f542aca090
Original-Change-Id: I938e227a142e43ed6afda80d56af90df0bae1b05
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19671
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506214
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Probe RAM to find its size instead of hardcoding 1024M.
Also properly export it to memory map.
BUG=none
BRANCH=none
TEST=none
Change-Id: I145291ef63afe8856e4a958f97853680f24af54d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7723133073
Original-Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/13754
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506213
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I762d8d2bb4bf23f0b6966c1fc752b16d254f2468
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b3456a9e80
Original-Change-Id: I99d0bd7d9b897a10edce35316e095e0223522c54
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Found-by: clang
Original-Reviewed-on: https://review.coreboot.org/19656
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/506212
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
from FSP release V030_61
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibc2f9d7a51c8428b95de74a672b36c1f2572fb5e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0435f97acb
Original-Change-Id: I5ecba08de851ee2e362f9ac31e1fa8bf3dfceebb
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19605
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/506211
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
BUG=none
BRANCH=none
TEST=none
Change-Id: If1d8dd58d2a9953a2d6318efcfecd8ce6d8a5425
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 12e6562289
Original-Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Original-Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19652
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506210
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4aec07bcaba5721297f432194310163d75925d7d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 267d086a08
Original-Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Original-Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19651
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506209
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
APU2 exposes a LPC header which can be used
in conjunction with a LPC TPM module.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie1c9be5d1e51d4f9f6aa64603c754dd3001bfeb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ca39df8195
Original-Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18523
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506208
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib2a34ccafd64aefcd9795e162a15a2fab3e15696
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 30670121c3
Original-Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18522
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506207
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaa49e89d54dd9688581460fbf4f64d2f51c7c4f4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5fd00ce71a
Original-Change-Id: Ic521b177b9602ff042312cccaaa89371db7c5855
Original-Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19071
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506186
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove overrides that set platform defaults or insane values.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7c8643a958ab7883392de59a82531312b4fcd58e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5f9fe7232a
Original-Change-Id: I11d1c7155bf1c7f9298f60638a6c2f3b128f3fe8
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19354
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://chromium-review.googlesource.com/506185
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This mainboard contains an external RTC chip RX6110 SA. Enable usage of
this chip and set some initialization values to device tree.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4a7eee24699c5f84bb11436281a7b3d37501ddb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3c4ddab1d4
Original-Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19647
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/506184
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This driver enables the usage of the external RTC chip RX6110 SA
(http://www5.epsondevice.com/en/products/i2c/rx6110sab.html) which is
connected to the I2C bus. The I2C address of this device is fixed. One
can change parameters in the device tree so that the used setup can be
adapted to match the configuration of the device on the mainboard.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ied233d7e24c60e475f4866df9fc5d2f0ade239e2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7fd20beaf8
Original-Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19625
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/506183
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The EC doesn't support it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I889b8d0ef04dadc4c7695c14197adf014279ab68
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a5fcc2e427
Original-Change-Id: Id2964002406a5fcf992f0ffc3627e3f66a2bb13f
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19654
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506182
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the
ThinkLight from the Operating System. This patch adds partial support for
that method, enough to enable or disable the ThinkLight:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
With the original BIOS the UCMS method exposes a wide range of values
through a generic /proc/acpi/ibm/cmos interface. With the changes suggested
in this patch that interface is also exposed but only accepts the commands
to enable or disable the ThinkLight; all other commands are ignored.
This change would potentially benefit all currently supported Thinkpad
models, I only have an X201 available for tests though.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id1345b20413a0dfd9834527b2b20faad2dccc75c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f63fbdb63a
Original-Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066
Original-Signed-off-by: Stefan Ott <stefan@ott.net>
Original-Reviewed-on: https://review.coreboot.org/19644
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506181
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
There are no GCC warnings anymore about set but unused variables, and
Clang warns about this switch, as it doesnt know it.
So remove the switch to use the default set by the switch `Wall`.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2b36e2f6e972a95014319d544735403bcf2081c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 10984d1034
Original-Change-Id: Ie9eb26d4f8b298af231b952b547b71d68c649eaf
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/19613
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/506180
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Only commented out code uses the variable `csr`, and GCC complains about
it, when enabling the warning *unused-but-set-variable*.
```
Checking for pciutils and zlib... me.c: In function mei_dump:
me.c:50:18: warning: variable csr set but not used [-Wunused-but-set-variable]
struct mei_csr *csr;
^~~
```
As the code is commented, also comment out the declaration of the variable.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id62ca6b6cacff775c2405993e7f7468b1abaa9f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 90d41779d1
Original-Change-Id: I4ecb2b5e9f32906ccfc8a0628d2e0f2d3ad39a02
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/19612
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506179
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I0e7e4ecb909d6f99a1cd1bc965b52694a8291e03
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d84a1cae09
Original-Change-Id: I05f768c67542770e65279a562c05225b84edca40
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19626
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/506178
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
BUG=none
BRANCH=none
TEST=none
Change-Id: I05077218d6e434d9c52a86cf53003959afca435b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 512a2d1c4f
Original-Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19650
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506177
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I58e973e472aa54b20b373c3a795516b1485f87d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1dcb2ac199
Original-Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19649
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506176
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I81abfe539a145d88017047d36c36cf6c54b65ae0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c5fba2c17c
Original-Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19648
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506175
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
On Ubuntu 16.04 the libpci-dev package is required.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1e96bc889ad52464ed715cb4e6540a794b106650
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0d2ff132e6
Original-Change-Id: I942b3e96f5b8112166a105eb5a61f8f3cf16cb7c
Original-Signed-off-by: Vincent Legoll <vincent.legoll@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19617
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/506174
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- set GPIO_183 to high level for enabling the power of SD card
- delete all GPIOs for JTAG interface because they lead to problems with
Lauterbach debug hardware
BUG=none
BRANCH=none
TEST=none
Change-Id: I684fc6815be9c49dc59ab326c491edd962c4f8a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4125dde2be
Original-Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19623
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/506173
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Promote DRVR_CAP_8BIT from controller specific to controller independent
TEST=Build and run on Galileo Gen2
Change-Id: Idc0beb17f28676c71a80da693fd27aeb7f8e7313
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 65d15c0f11
Original-Change-Id: I51e4c990d3941a9f31915a5703095f92309760f1
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19642
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506172
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix bug detected by coverity to handle the zero capacity case. Specific
changes:
* Reduce loop count by one to handle zero capacity case
* Use structure instead of dual arrays
* Move structures into display_capacity routine
Coverity Issues:
* 1374931
* 1374932
* 1374933
* 1374934
TEST=Build and run on Galileo Gen2
Change-Id: I4784d261fbaaf707f3782a32993c1eca01944d15
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bf5d5093fc
Original-Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19643
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/506171
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
s230u seems only have two sata ports: one for the 2.5in hdd and one for
msata. map 0x11 (port 0 & 4) enables hdd but not msata, and map 0x5
(port 0 & 2) enables both.
BUG=none
BRANCH=none
TEST=none
Change-Id: I11aba1d95e53ffc8e97c152bf6aa6b01d299820f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 72f730e23c
Original-Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19523
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/506170
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove unused field in generic SD/MMC controller data structure.
TEST=Build and run on Galileo Gen2
Change-Id: Icc3b0a6856e6454a2db45cf44cf01e3c2dada95e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1c1c071b88
Original-Change-Id: I7169dca07509a6f2513d62b593742daf764010b2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19629
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506169
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Is only present on the P45 subtype of chipset.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac30ec9f12a559730bf3e786301d7f5882caff52
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 293445ae1f
Original-Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18516
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506168
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
BRANCH=none
BUG=b:36666655
TEST=boot from bob, tested with memtester/s2r/reboot on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Original-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19558
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488421
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
BRANCH=none
BUG=b:37262721
TEST=mem checks the register value on bob.
localhost / # mem r 0xff76004c ---> 0x00000100
localhost / # mem r 0xff760050 ---> 0x00000860
TEST=Tested with memtester/s2r/reboot on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Original-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19557
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377691
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Tested against a lenovo-manufactured tpm 1.2 module:
a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in
SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards.
BUG=none
BRANCH=none
TEST=none
Change-Id: I81485ce4f64e0e58a3204052a314cf20c6eaa439
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dcb789da9
Original-Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19521
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/501164
This replaces the custom environment controller handling in the it8728
driver with the common library.
It also updates the two existing boards with hwm register settings in
their devicetree config so they better match their vendor BIOS fan
control settings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I200629a1d69e39ba9b5f7fdb9801fc4df5c320e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f064d7551
Original-Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/19293
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/501163
BUG=None
TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I9b70609a74d70856fc3aa72250f9ff1bc240af0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 709bc6eada
Original-Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/19479
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501158
According to "Intel 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic71a7c81d494e91f4aee97fe489a4df29b99843f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e3cb72a71
Original-Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18515
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/501157
The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibd9669589a05f5ec776c3f9bc81de65266ced83e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e7efe65a2
Original-Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19607
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501156
