The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
BUG=none
BRANCH=none
TEST=none
Change-Id: I0912069553813210587354ce181942f5974eed4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 70d92b9465
Original-Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19377
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/517933
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add more fine-grained details about what device caused the PME wake
event. This requires checking the PME status bit (bit 15) in PCI PM
control and status register for the PCI device.
BUG=b:37088992
TEST=Verifed that XHCI wake source was identified correctly:
135 | 2017-05-25 15:28:17 | ACPI Enter | S3
136 | 2017-05-25 15:28:26 | ACPI Wake | S3
137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0
Change-Id: Ieef07a972d2a610284df082109a5bda59ab10dba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ef8bb9136e
Original-Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19925
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517932
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is required to add wake sources for PCIE PME events.
BUG=b:37088992
Change-Id: I46f4b244510ba5201566a4cd2c7e2e205b065137
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1cf7f86d92
Original-Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19924
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517931
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add wake sources for PME events generated by different devices.
BUG=b:37088992
Change-Id: I05b212d6043b50588d54d7069db76ce89f3459e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b858157dba
Original-Change-Id: I25098f489f401148171c235cb341f6e7bb2b635b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19923
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517930
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Not all systems have sizeof(time_t) == sizeof(long), so
cast the delta here to a long to match the %ld format.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic398f319b1711f32e4e2c0b579d2fc858084f714
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8ca03223a
Original-Change-Id: If235577fc35454ddb15043c5a543f614b6f16a9e
Original-Signed-off-by: Mike Frysinger <vapier@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19902
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517929
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch fix rk_mipi_dsi_phy_init error return.
BUG=none
BRANCH=none
TEST=none
Change-Id: I731277cde56270bcf18f97dc5c9a0eacbaa12121
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5be0b2e03d
Original-Change-Id: Ie260975ad6ed26c37aa8bb65dfcef4db2407a2da
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19903
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517928
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I45a8b5be4e26b1edfd42bac86daf1e98b19bd781
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6b697ef207
Original-Change-Id: Iac4cdb003b2fe967b303c1f8e0eeb61673a02858
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19930
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/517927
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
hugo has no need to write there, it should only write to the
output directory.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icac77298ae86d06bdeb350706e207c3e6c4d664f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dc5eea1cfa
Original-Change-Id: Ie320f5017feccfa2e9ecba3c802e040487b44d67
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19929
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/517926
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.
BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.
Change-Id: Ibae8907f260b50eb0d1283f26294fb73e963d051
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 73108ded48
Original-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19829
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517925
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
www.coreboot.org/Documentation is now built with hugo (www.gohugo.io)
based on files in this repo's /Documentation directory.
Also clarify that new additions to Documentation are under CC-BY 4.0 terms.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iedadababa4129d983118eb9a59f93d3fa3a4bb0c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 04edaefad7
Original-Change-Id: I000e15b29a182bb88b40de3d0178bf8cc54ba8af
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19881
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/517924
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Namely png (images) and eot, ttf, woff (fonts)
BUG=none
BRANCH=none
TEST=none
Change-Id: I34654dcc6c7f4b6eae00c69c55d58b6b012fce20
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9ec25f7678
Original-Change-Id: I41e773c0adab796876a3b1e91e089ae89cbb04df
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19880
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/517923
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
API functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
In addition to the API functions above, helper functions are added to
gpio.asl to set/clear/get Tx value of GPIO.
BUG=b:62028489
Change-Id: Ie79dcb9c4b57bfe435d173310025577a947509ac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a6f0b2754b
Original-Change-Id: I77e5d0decd8929a922d06b02312378f092551667
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19828
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/515866
Commit-Ready: Shelley Chen <shchen@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of storing inverted-colored bitmaps,
invert drawing of text bitmap on the fly by adding
an invert parameter down to libpayload. Merging
pivot and invert fields into flags field.
BUG=b:35585623
BRANCH=None
TEST=Make sure compiles successfully
Change-Id: Ie397160b54f488abd7260332ee26d0b5140584bb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d635506fa7
Original-Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19698
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/515865
Commit-Ready: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Should result in a tiny speed bump in raminit since those addresses
are not checked for present DIMMs.
Checked in schematics of both Thinkpad X60 and T60 and tested to
configure raminit correctly for all DIMMs populated on X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib52cde02578aa34de55be6e9b482ba47019b9809
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 000cc598cb
Original-Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19862
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/515864
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I355a6b7527743f863e1fa34d52bca28506975aa9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 36dafd88bc
Original-Change-Id: Ia44097f32f74ffd749219415984224ce33d9252b
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19816
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/515863
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
It seems that the BootROM on the RK3399 overwrites some of the earlier
parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have
a persistent CBMEM console we want that area to survive in case of an
early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it
further back. (This reduces the stack size to 12KB which should still be
way more than enough.)
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac2a886490fbd53c9655ea9edb5df89bae9a37b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 34dba35831
Original-Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19784
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/514193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Soraka uses OV 13858 sensor. Hence update the same.
BUG=none
BRANCH=none
TEST=none
Change-Id: If48f4c2411f2450f2d617b342c587ccf5675a51e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b25b2329a9
Original-Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19639
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
It could end up not initialized which causes it not to build with
clang.
BUG=none
BRANCH=none
TEST=none
Change-Id: I295a03b36c881c157fd8ae00cace1686d67089ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 37689fae38
Original-Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19736
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD),
it displays wrong part number during boot in coreboot logs.
So correct part number info within the SPD.
TEST= Build for Soraka & make sure part number is rightly printed.
Change-Id: I6ab2b81223364c7e48e9d64e080f459c27843d09
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1d407cceaf
Original-Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19692
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/514190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Now that all platforms are updated to provide spi bus map, there is no
need to keep the spi_setup_slave as a weak symbol.
BUG=b:38430839
Change-Id: I9b4b8a600b5b6de3b2ec9956f24f09eaa4b2a321
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd8d24759d
Original-Change-Id: I59b9bbb5303dad7ce062958a0ab8dee49a4ec1e0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19781
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/514189
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
No mainboard is actually using this SoC. Remove the code for this SoC
for now.
BUG=b:38430839
Change-Id: If7034ff7d092b2935519b54c6267abe9ea0f7f21
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 53bbf87a4c
Original-Change-Id: Ia35986dffda8bbd76305ef5abab6ae81cc154b0f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19824
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/514188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ia7c95879b7c96f8ed0913959f587f7deefe62dec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 12eca76469
Original-Change-Id: I2a789cff40fb0e6bd6d84565531d847afb3f8bed
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19780
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I269ad36b81a4365807d036038d16de2d5077f253
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2cd03f1696
Original-Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19779
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514186
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ib2484bdf3e8a45eefc46c71ae4c52fb7d07ff6bb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2d9a99535d
Original-Change-Id: Id3f05a2ea6eb5e31ca607861973d96b507208115
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19778
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514185
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I76ceda11937839f758cd7c2b48f9164c5ee5d109
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f8662ca3bc
Original-Change-Id: Ic937cbf93b87f5e43f7d70140b47fa97bcd7757e
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19777
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514184
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ie955c903e299be8ff49e73b68c16b37ff833188c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e424a59729
Original-Change-Id: I6cc8c339e008e16449fa143c1d21e23534bdaf0b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19776
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/514183
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I4a3b46bd16c8f384e76a38817fce86318c5be516
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 56c88ebc02
Original-Change-Id: I48b242dd6226e392ed0f403051843b3ae02cd9a4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19773
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514182
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I8d8cf520a53cd74d50ce658aacd0cb59ac8f0438
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e173ee8f01
Original-Change-Id: Ie4ec74fccaf25900537ccd5c146bb0a333a2754c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19772
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513961
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ief26dec8c156ce1fbc87cab0f3504c091d7c048c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 23d5d99098
Original-Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19771
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513960
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I5cce241a0726571f522f69d3bfec7c18d621e6e3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 02c0743a24
Original-Change-Id: Ib0d6e4e8185ce1285b671af5ebcead1d42e049bc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19770
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513959
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I1d10c535ad7d5bb8545e9ad463b9938ed2cff4f1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b46e9f6029
Original-Change-Id: I873b96d286655a814554bfd89f899ee87302b06d
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19769
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513958
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The SoC code was never completed. It's just a skeleton that gets
in the way of refactoring other code. Likewise, the mainboard was
never completed either. Just remove them both.
BUG=none
BRANCH=none
TEST=none
Change-Id: I19d42549463e9726bcd4bcd119634733a933e184
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 250715eb2f
Original-Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19823
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/513957
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add support to the Intel common firmware Kconfig and Makefile.inc to
allow the embedded controller (EC) blob to be added to the final
binary through ifdtool.
TEST=Add ec.bin and enable in config, build is successful.
Change-Id: Ic4cc8d05f5cc6a303fe33807cf99c3081ac87dba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0fb6568444
Original-Change-Id: Ib14732b4d263dde4770bf26b055c005de2540338
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19719
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513956
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Field Programmable Fuses (FPF) status maintained by
CSME in bits 30:31 of FWSTS6 for Skylake and Kabylake.
FPF committed means CSME has blown the fuses.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3db6962e0e70038430c774b781cb55b3d069973f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4a907c79a2
Original-Change-Id: If63c7874e6c894749df8100426faca0ad432384b
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19747
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513955
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia9167fc82c36d2e1ae2a681418dea2d91a544c78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f714965e8d
Original-Change-Id: I08dd7a8c0d42d4ec7c6ff65a82553fe1efbcc424
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19687
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/513954
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add GLK PCI IDs for I2C to use common I2C code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I594ddafbab9ee64f5cb2f8e7732784ea466a0d19
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3038e9bd08
Original-Change-Id: I2144199345e6382984c367f6a77f0cbb0a93daea
Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19782
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513953
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.
BUG=b:38436041
TEST=Verified that elog entries are updated correctly:
Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode
Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0
Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0
Change-Id: Ic052854ef87fc88d4c25b6d14b8deb4fafe1f0fc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7941c96f8e
Original-Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19798
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513951
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is useful for debugging based on eventlog to identify if platform
entered normal or deep Sx.
BUG=b:38436041
Change-Id: Id63cf4d97126770e2a32a508d10ae5aff0d3e32b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 75ef6ec29e
Original-Change-Id: Ic7d8e5b8aafc07aed385fe3c4831ab7d29e1f890
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19797
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513950
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use SATA common code from soc/intel/common/block/sata
and clean up code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I26f5ca6de3d9cbaa09faac09bbc86ecf3402cde3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fd8e00092a
Original-Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19735
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510781
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add SATA code support in intel/common/block to initilalize
SATA controller, allocate resources and configure SATA port
status.
BUG=none
BRANCH=none
TEST=none
Change-Id: I53190966c44685573e636375444b471a6dec0f22
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1b1ecae0a4
Original-Change-Id: I42ec0059f7e311a232c38fef6a2e050a3e2c0ad3
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19734
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510780
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add PCIe code support under soc/intel/common/block
to initialize PCIe controller, allocate resources
and configure L1 substate latency.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifccff937795c9b1f710c527c0d3816b3e4731486
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2d689f9e0d
Original-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19665
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510778
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I72a8270841ec229a2e27be71f3a6b3262640e6f1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4bbfe57959
Original-Change-Id: I6e710b95cade0ea68f787f33c0070613d64b6da6
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19743
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510777
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I781280dad7477dd55788db2e487e20f4ec911b33
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 10326ba889
Original-Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19801
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510773
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove guards and let the linker take care of it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I88864bb4de1b4185efb8ea8d42c61882dda1caf5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bb72852baf
Original-Change-Id: I96ad8002845082816153ca5762543768998a5619
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19744
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/510772
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
