Commit graph

45 commits

Author SHA1 Message Date
Stefan Reinauer
1a5f05b02c rename VM86 to REALMODE in v3, too, as that is what it really is.
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1171 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-06-07 17:36:43 +00:00
Mart Raudsepp
cb5d9d3867 cs5536: Remove redundant enable_ide variable from ide device.
The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form.
cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't
exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not
necessary.
Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole
IDE device removed, which results in the ide_init() code not being ran as before (before it was called but
early return from enable_ide == 0, now it won't be called in the first place).

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-09 18:12:08 +00:00
Myles Watson
13765fd116 This patch updates geodelx to fit the new resource allocator better. It
splits the domain and the memory controller functions into their respective
devices.

It also updates the dts for all the boards that use geodelx_video_mb.

Signed-off-by: Myles Watson <mylesgw@gmail.com>Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1103 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-07 18:26:18 +00:00
Corey Osgood
758fecb860 Move OPTION_TABLE to a menu config option, and default it to enabled. This allows
a user/developer to disable the option table, so it doesn't overwrite whatever
the factory BIOS has written. Also fix building with OPTION_TABLE disabled.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1078 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-18 02:00:55 +00:00
Peter Stuge
35b5759efb Remove insignificant unused spd_devices arrays.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1011 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 01:04:35 +00:00
Marc Jones
607e6aff43 LPC serial IRQs were being left enabled when there is no LPC serial device.
Signed-off-by: Marc Jones <marcj303@yahoo.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@986 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-07 00:51:38 +00:00
Uwe Hermann
8e6d45e059 Minor fixes and improvements for v3, mostly for Kconfig files (trivial).
- Coding style and whitespace fixes.
 - Remove obsolete comments, fix incorrect ones.
 - Use the full/canonical name of mainboards/vendors everywhere.
 - Update the list of USB Debug capable chipsets from
   http://www.coreboot.org/EHCI_Debug_Port.
 - s/LB/CB/ for the CONSOLE_PREFIX kconfig option.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 18:29:22 +00:00
Carl-Daniel Hailfinger
67accc1f69 Fix Kconfig dependencies and update defconfigs.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@784 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 16:48:27 +00:00
Carl-Daniel Hailfinger
1b22622323 Change v3 makefile rules to be source-based, part I.
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.

This pepares the way for additional optimizations during compile and
link time.

Build tested and boot tested on Qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 11:15:43 +00:00
Carl-Daniel Hailfinger
fe0147c155 CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill
it. Since it was the only content of the i440bxemulation northbridge
Kconfig, kill that file as well.
The i440BX RAM size is determined from the dts and the chipset specified
size is ignored. Print a warning for that, especially because v2 uses
the chipset specified RAM size.

Build and boot tested on qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@766 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-15 16:41:37 +00:00
Carl-Daniel Hailfinger
1a09707fd6 Convert stage2 and initram makefile rules from object to source files.
This creates a clearer distinction between source files in the source 
tree we want to have compiled and indirectly created object/source files 
in the object tree.

It also will make enable us to move to whole-program 
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as 
well.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 20:56:11 +00:00
Carl-Daniel Hailfinger
03dca375db Right now, our Kconfig files in the mainboard/ directory in the v3 tree
are not exactly in the best shape.
- MAINBOARD_NAME is claimed to be the mainboard name, but it is used 
  exclusively as mainboard directory.
- MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to
  $VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes
  $VENDOR/$BOARD as board path.
- MAINBOARD_NAME has a help text which will never be displayed to
  the user.

The diffstat is encouraging: A total of 200 lines have been
removed completely.

Per-board Kconfig files have been deleted, the remnants making sense
have been merged into per-vendor Kconfig files and the never-shown help
texts have been removed.

If there are ever some real per-board options and not just tricks to
make the makefiles behave, we can resurrect the per-board Kconfig files.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@705 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:40:22 +00:00
Ronald G. Minnich
2f5d7b66a9 1. fix dtc to properly put @x,y in hex, not decimal.
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-30 15:08:25 +00:00
Ronald G. Minnich
96914e1655 1. geodelx.c: cover case of unterminated DRAM by adding a terminated
parameter to two functions. 
2. geodelx.h: define DRAM_TERMINATED and DRAM_UNTERMINATED constants
3. dbe62/initram.c: move to auto PLL control, so set MANUALCONF to 0
4. all other initram.c: set up calls to cpu_reg_init with proper 
   TERMINATED/UNTERMINATED constants. 

builds for dbe62. The auto PLL strapping is tested and works. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@699 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-29 15:54:46 +00:00
Carl-Daniel Hailfinger
b1596f216b Rename mainboard_part_number to mainboard_name in various places. This
is the logical continuation of r416 which happened a year ago.

As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.

Build tested on all targets. Patch attached for Gmail users.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-20 21:05:25 +00:00
Carl-Daniel Hailfinger
a4b90bacf4 Makes mainboard-vendor naming more consistent.
mainboard-name naming has been postponed because it's not clear what the
real name should be.

Generated code is identical to the state before the patch.
Compile tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-11 12:33:46 +00:00
Ronald G. Minnich
dc231a7041 This is the fix for MFGPT on those boards which have a cs5536 and ALSO
have a superio.
With this patch, alix1c and MFGPT work fine. Still need to test on Alix2c3, but it
is likely it will work.

Thanks to Marc and Jordan for this one.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@682 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 21:48:28 +00:00
Ward Vandewege
e31836b6af This puts USB and eth2 on IRQ 11 (eth1 was already on IRQ 11). This makes the
kernel much happier.

As Marc suggested, having these devices all on the same IRQ seems to be fine.
I've tested performance - I get 11MB/sec copying data from eth2 to eth1, as
well as from eth2 to eth0 (which is on a different IRQ). That's 90% of
wirespeed which is what I'd expect to see.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@680 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 14:00:57 +00:00
Carl-Daniel Hailfinger
4ab20cb518 Move CS5536 IDE configuration into a separate dts and its own PCI device.
Fix dbe62 IDE/NAND selection.

Build-tested on db800, norwich, dbe62, alix.1c, alix.2c3.
No additional breakage for dbe61.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@677 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-07 23:21:55 +00:00
Ward Vandewege
7eebe3ffb2 00:0f.3 is the audio device, not usb. Also some whitespace cleaning.
All of this is applies to comments only.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@675 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-04 20:08:31 +00:00
Ward Vandewege
df60eea846 The default config (used by buildrom) should not have a payload defined.
Buildrom handles that.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@665 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-19 14:29:56 +00:00
Ward Vandewege
b68f1ac979 Add pcengines alix.2c3 support.
There is still one outstanding issue - eth2 and the USB ports fight over IRQs.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@663 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-17 17:27:13 +00:00
Ward Vandewege
2dc8f8ec2f We need a defconfig file for the alix.1c under v3.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@656 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-05 00:09:29 +00:00
Carl-Daniel Hailfinger
a23b525d0a PIRQ table cosmetics/cleanup. Bugfixes and #error for uninitialized
memory accesses.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@637 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-03-07 01:20:36 +00:00
Ronald G. Minnich
718dab6ba5 This is a cumulative set of fixes for LX800 boards. These are all tested on ALIX 1C and DBE62.
This includes:
 - the working power button patch.
 - onchipuart2 for very early startup -- this will be replaced with a better mechanism soon.
 - dts mod for powerbutton on cs5536
 - dbe62 dts fix for COM1 setup
 - ram check call in dbe62 initram.c
 - Carl-Daniel's fix to detect incorrect access to spd variables.
 - more debug prints in geodelx northbridge support code.

 This is cumulative since we're lagging on acks a bit and it's hard to keep this
 stuff all seperated out since it involves a common set of files. I'd like to get
 it acked and in tree today if possible. It's a very small set of lines changed so please
 forgive me for the cumulative nature.

 Thanks

 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>


Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>






git-svn-id: svn://coreboot.org/repository/coreboot-v3@636 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-03-06 23:33:59 +00:00
Ronald G. Minnich
9c2060a5e5 Factor out write_pirq_routing_table() for all GeodeLX targets.
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.

svn is unable to create a valid patch for what I did, so I'll have to
commit this myself. To reproduce, perform the following commands, then
apply the patch:

svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h
svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h
svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h
svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

tested on alix1c. Boots, USB, graphics, and ethernet all work.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@628 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-03-01 21:33:51 +00:00
Ronald G. Minnich
451f1fcbc6 Get rid of the conditional; this board always has PIRQ tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@626 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-29 16:53:34 +00:00
Ronald G. Minnich
775f57d4c3 Convert all boards using fake SPD entries to struct spd_entry, thereby
making sure we return 0xff for nonexisiting entries and shrinking the
data structure by 85%.
As a bonus, the various initram.c for boards with fake SPD are now
almost identical.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Tested on Alix1c, with minor mods to get it to compile. Full boot to 
Linux, with graphics. 

Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@622 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-27 05:27:51 +00:00
Ronald G. Minnich
902e96a640 Fix Geode graphics init. The functions to enable graphics were misplaced
in the pci dtc instead of the correct location in the domain.

Also fixed up some warnings on the const gliutable.

Tested on alix1c and boots to Linux, ethernet works. Still trying 
to light up the display :-)

Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@617 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-23 16:31:50 +00:00
Ronald G. Minnich
14c3feacff This adds support for AMD graphics initialization.
Note: You MUST have the later AMD VSA code that does not call bios 
interrupts. If you use the older code, your boot will hang at this 
point:
buf[0x20] signature is b0:10:e6:80
Call real_mode_switch_call_vsm

With post code 10

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@616 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-22 01:58:09 +00:00
Carl-Daniel Hailfinger
9b934a661d Update mainboard dts files to new style. Untested, but I tried to keep
the new settings as close as possible to the old settings.
All GeodeLX-based boards now include the geodelx/domain, geodelx/apic 
and geodelx/pci dts files.

Remove "enabled" keyword from the alix.1c main dts. (That's the only 
possibly critical change because it affects a working target. Tests on 
hardware appreciated. Should be harmless, though.)

Compile tested only for msm800sev, norwich and dbe61, and the situation 
is better than without the patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Tested and boots a working linux on alix1c.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@607 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-18 01:43:50 +00:00
Ronald G. Minnich
f7ad196c0a This started out as a trivial change and turned into a big change. This
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which 
will come once this is in. 

This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did 
not work out, and it revealed a flaw in the design. The result? 

- no more ids in the various dts files. 
- the constructor struct is gone -- one less struct, nobody liked the
  name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead. 
- lpc replaced with ioport

All the changes below stem from this "simple" change. 

I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!

TODO: 
1. Change limitation in dtc that makes it hard to use hex in pci@
notation. 

Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.

I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c, 
so I suspect one of today's "clean up commits" broke something. 


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-16 04:13:44 +00:00
Ronald G. Minnich
0044d53a10 This set of changes creates irq tables for alix1c and adds the functions
from v2 to install them. Linux boots fine and all interrupts
seem to work correctly -- the network comes up, USB hot plug works, 
I can mount the USB disk, etc. 

To enable pirq tables for a given mainboard, simply add the 
select PIRQ_TABLE (see below) to the Kconfig for that board. 

Again, this code builds and boots linux on the alix1c.

I think, with this change, we are very close to moving ALL LX boards to 
v3 and deprecating v2. The major remaining fix is to add an empty LAR 
entry to fill empty space in LAR and speed up the LAR file search 
process. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Index: include/tables.h
Add prototype, conditioned on CONFIG_PIRQ_TABLE

Index: util/x86emu/vm86.c
Comment out 'debug trap' code that scribbles vectors at 0x4000. 
I don't know why this is here, but I'd like to leave it #if'ed out --
somebody, at some point, thought we needed it. To reenable, we will need
to move stage2 code or these magic vectors. 

Index: arch/x86/Makefile
Add support for conditional compilation of pirq support code. 

Index: arch/x86/pirq_routing.c
Add this file from v2. 

Index: arch/x86/archtables.c
Add call to write_pirq_routing_table (controlled by #ifdef
CONFIG_PIRQ_TABLE)

Index: arch/x86/Kconfig
Add new config variable: PIRQ_TABLE

Index: device/device.c
Fix some trivial bugs. 

Index: mainboard/pcengines/alix1c/Makefile
Add pirq table code for stage2

Index: mainboard/pcengines/alix1c/dts
Modify dts to properly set southbridge variables

Index: mainboard/pcengines/alix1c/irq_tables.c
Add code from v2 for the alix1c. 

Index: mainboard/pcengines/Kconfig
Add 'select PIRQ_TABLE'

Index: include/arch/x86/pirq_routing.h
Add include file from v2.
Remove all the SLOTCOUNT nonsense. This hack was only needed
for a very early version of gcc 3.x, where they screwed up the 
creation of struct members that used the [] syntax for variable-length
array at the end of the struct. 

Index: include/device/pci.h
Add prototype



git-svn-id: svn://coreboot.org/repository/coreboot-v3@582 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-09 16:32:59 +00:00
Ronald G. Minnich
010f751a48 With this set of changes FILO now reliably finds the IDE controller.
Press <Enter> for default boot, or <Esc> for boot prompt...  
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200
malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks)
malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks)
file_open: dev=hda1, path=/vmlinuz
ide_probe: ide_probe drive #0
ide_probe: ctrl 1188096 base 0
find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80
find_ide_controller: primary channel: compatibility mode
find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4

Sadly, it locks up at this point, but this is still progress.

I realize the location of the defines is a little odd, but I think it is useful to have 
them right next to the function that uses them. 

Index: southbridge/amd/cs5536/cs5536.c
cs5536.c: add ide support functions from v2
Index: mainboard/pcengines/alix1c/dts
Correct error in southbridge pcipath. Add enable_ide to dts. 
Index: southbridge/amd/cs5536/dts
Add dts for enable_ide.


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@575 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-07 06:33:49 +00:00
Marc Jones
5917206641 Cache the ROM to speed up stage2 and payload decompression.
Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below.

Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1.

Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload().

"The problem is a transaction depth issue and bottlenecks inside the GX
and LX that go across PCI.  The conditions are very complicated but it
comes down to we need write serialization for writes to PCI. If you
look in the data book you can't have write serialization and the cache
enabled on a given area. During coreboot we don't have to worry about
a write or a PCI bus master so I think we can enable caching the ROM.
After coreboot we can't be sure what will happen in the system so we
need to set it up to be safe. For example flashrom just clears the
write protect bit. If the cache were enabled (no write serialization)
and flashrom was writing the ROM we would be in a precarious position.
A PCI  bus master doing a read or a write that has a hit on a tag
would cause enough bottleneck conditions that it might hit the bug. We
could change flashrom but that doesn't help other tools. We need to
leave the system in a safe state. Also, caching the ROM after it is no
longer used doesn't make much sense. So, we need a call just before
the payload runs to clean up the system."

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-06 02:36:50 +00:00
Ronald G. Minnich
ce5a0d5574 with VSA operating correctly. This is tested with AMD's recently
released new-model VSA code. 


Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.

Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.

Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.

Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the 
domain AND the PCI device, which is a mistake: can't scan from the 
PCI device too. 

Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.
Created via svn move dts domain

Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error, 
since there are 
some no-pci devices in the tree now. For future: only complain about
leftover PCI devices ...

Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk. 

Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean
to me, the way it went in. 

Index: northbridge/amd/geodelx/vsmsetup.c
Delete all pcibios int support, no longer needed for VSA. 

Please note that this patch includes Carl-Daniel's improvements 
below, which I have Ack-ed. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

A few minor comments. It would be great if you could address them before
committing.

northbridge/amd/geodelx/domain is a copy of northbridge/amd/geodelx/dts.
You probably want to use "svn mv" for that because it preserves history
and the old file was probably intended to have been moved, not copied.

northbridge/amd/geodelx/vsmsetup.c:247: warning: ‘biosint’ defined but
not used
Since the new VSA does not use BIOSINT services anymore, deleting
biosint and related functions from vsmsetup.c would shrink vsmsetup.c by
one fourth. Patch follows (could you merge it into your patch?):

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@571 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-01 20:35:53 +00:00
Ronald G. Minnich
57ea42fab8 Fix compilation after switch to explicit dts naming.
One additional cosmetic fix. 

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@569 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-31 03:08:32 +00:00
Stefan Reinauer
6220b632e7 Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-27 18:54:57 +00:00
Ronald G. Minnich
22a005f670 This change adds a dts file for the amd geodelx northbridge. The
northbridge has several constructors, so it is required, if these 
constructors 
are to be compiled in to the running image, that a dts be provided. 

To use the dts, one must add a /config/ line to the components 
that use it, hence the change to the mainboard dts .

This change does not produce a working bios as far as I can tell. 
But it is still important to have it in. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@555 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-17 05:37:41 +00:00
Ronald G. Minnich
9b1d2f4978 This is a trivial patch to correct a spelling error in a comment.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@542 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-12-11 01:24:52 +00:00
Carl-Daniel Hailfinger
aa9bb6e81b Absolute calls from initram were only working from the file which had
_MAINOBJECT #defined. Calls from all other files ended up in nirvana
because the compiler was not able to calculate the address of the
wrapper for the absolute call. The linker tried, but failed miserably.
Use the -combine flag and compile all of initram at once. This enables
GCC to calculate the address of the abscall wrapper, resulting in
working code.

Segher Boessenkool thinks the patched code works only by accident
because GCC has no way to specify generation of XIP code. According to
him, future GCC versions or other circumstances may break the code.

While this patch makes code work for now, it does NOT check whether the
generated code tries to write to memory outside the stack (general
writable data). That will of course fail, but I hope porters are smart
enough to avoid that.

Corey Osgood writes:
Great work tracking this down! This is okay for now, but we need to look
for a better solution in the future. Counting on porters who may or may
not remember this discussion to avoid something isn't good
future-proofing.

Checking the ELF sections for read-write data and stopping the build
with an error could make this future-proof.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@537 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-12-04 22:42:38 +00:00
Carl-Daniel Hailfinger
210463d65c Factor out one identical makefile rule from all mainboard makefiles to
the x86 arch makefile. This makes porting to a new mainboard less
confusing.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@529 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-27 19:06:45 +00:00
Ronald G. Minnich
2bae97c52f This gets as far as pll_reset and dies.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@525 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-27 16:19:34 +00:00
Carl-Daniel Hailfinger
7eb899b0bb Use the elf-parsing capabilities of LAR to parse the initram.o file,
and create a valid LAR header with an entry value. This will fix the
problems Ron is having on the ALIX 1C and probably allow it to boot.
It also sets the text base of the .o to 0, instead of whatever wacky
value gld is choosing, so all platforms will have the same value.
Get away from worrying about potential gld bugs, now and in the future.

As added benefit, we obsolete a lot of code without introducing
new code.

Qemu target entry point debugging has been added to be able to spot
problems with entry points in the future.

This patch is a joint work of Ron and Carl-Daniel.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@523 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-27 14:38:43 +00:00
Uwe Hermann
9d16f2066e Initial support for the PC Engines ALIX1.C board.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@521 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-26 22:12:12 +00:00