2 size calculations.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
that has already been done by the BSP. For single processor systems the CPU
flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to
after memory setup so the AP's MTRRs can be setup to match system memory.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
have a CAR area outside the usual RAM area. For those processors, we
have to implement a stack copying and switching mechanism. Since gcc
can't be told that the stack just moved, split stage1_main() into
stage1_phase1() and stage1_phase2() and stage1_phase3().
stage1_phase1() is the new entry point in stage1 and will handle
everything up to the point where we want to disable CAR.
Switching the stack, disabling CAR and handling other tasks related to
the stack switch (printk buffer move) is all wrapped in the
stage1_phase2() function.
stage1_phase2() calls disable_car() which then calls stage1_phase3().
stage1_phase3() is the former second half of stage1_main().
Notes about this patch:
- Code flow is almost unchanged for Qemu, K8 and Geode. No extensive new
testing required.
- We can support stack-keeping and stack-relocating architectures at the
same time, so C7 is definitely supportable
- The comment in stage1_phase2 says "some of this is not yet done". That
refers to the nonexisting code for stack switching on C7.
- "Minimal changes, maximum benefit".
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@932 f3766cd6-281f-0410-b1cd-43a5c92072e9
implementations. Factor out the 16 bit code with associated protected
mode activation.
I'm open to moving even more common code out, but this is a well-defined
start.
This cleanup has been prepared for by r902, r905 and r907.
Boot tested on qemu. Build tested on i586, geodelx, k8.
The diffstat is most enlightening:
amd/stage0.S | 145 ---------------------------------------------
geodelx/stage0.S | 145 ---------------------------------------------
i586/stage0.S | 145 ---------------------------------------------
stage0_common.S | 145 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 148 insertions(+), 432 deletions(-)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@908 f3766cd6-281f-0410-b1cd-43a5c92072e9
CAR code.
Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order.
Now we can split out the common parts more easily and concentrate on the
differences.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@907 f3766cd6-281f-0410-b1cd-43a5c92072e9
except for the actual CAR code and inital #includes and #defines.
Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order to the best variant
present in the 3 files.
Now we can split out the common parts more easily and concentrate on the
differences.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@905 f3766cd6-281f-0410-b1cd-43a5c92072e9
byte-for-byte identical. That makes factoring out easier.
Fix a duplicated BIST save for K8.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@902 f3766cd6-281f-0410-b1cd-43a5c92072e9
We need to figure out if we should just grow stage0. My inclination is
to say 'yes'.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
moved to stage1 ROM code. Make the struct for nodeid/coreid generic to
x86. Create the functions for existing architectures are a model for
future architectures (VIA coming soon we hope).
Move includes so that things build correctly now.
This is actually a small patch that impacted a number of files due to
include order changes. This is build and boot tested on simnow and
build tested on geode.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@872 f3766cd6-281f-0410-b1cd-43a5c92072e9
AMP TinyGX still builds, this won't affect other platforms.
clean up 8111 stage1 code; add function to smbus,
memreset_setup_amd8111, for the 8111 specific parts of memreset.
include k8 .h to reduce warnings. Turn some things into functions (romcc
legacy cleanup) and put them in .c files.
simnow actually successfully gets through a reset cycle now.
Next is to fix the fidvid code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@868 f3766cd6-281f-0410-b1cd-43a5c92072e9
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
but that's not something we should rely on.
The new code is entirely rewritten, fixes a few missing constraints in
the asm and should be a lot more readable. However, the generated code
is NOT identical. The old code was broken because of the missing ecx
clobber constraint and it did not copy the stack back (ecx was zero at
the beginning of the copy-back loop and so the loop executed exactly
zero times).
So this is a genuine bug fix.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron writes:
wow! nice catch!
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
We also need disable_car_and_halt, which only disables car and halts,
for the APs (i.e. no need to copy stack back)
git-svn-id: svn://coreboot.org/repository/coreboot-v3@858 f3766cd6-281f-0410-b1cd-43a5c92072e9
which point we hang:
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0
pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0
pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0
pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0
pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0
ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0
domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: PCI: 00:04.0 init.
The dts is quite incomplete and that is part of the problem. Doubtless
there are other problems :-)
But training is indeed working in simnow, and memory is working, and we
can return from disable_car as on the geode.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@855 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@851 f3766cd6-281f-0410-b1cd-43a5c92072e9
There is really strange logic in the init_cpus, and it needs cleanup.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@849 f3766cd6-281f-0410-b1cd-43a5c92072e9
This code has been tested on dbe62, and builds for qemu as well.
the next step is testing on simnow.
k8.h: add more prototypes and some required inline functions.
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
used for coreboot.
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
what you get are warnings.
There is lots of room for improvement as we move to all CAR
code, but that will take time.
I hope to get this to really compile over the weekend.
At the same time, if anybody wants to take a crack at it, your efforts
are welcome.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@843 f3766cd6-281f-0410-b1cd-43a5c92072e9
legacy. Use constants as much as possible instead of magic numbers. Set
up common prototypes in an include file.
The fidvid needs major cleanup but this code is so tricky I don't want
to start cleanup until I feel it is more or less working.
Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Ronald G. minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@841 f3766cd6-281f-0410-b1cd-43a5c92072e9
If anyone wants to review my comments, or maybe even try to fix compile
issues, have at it :-)
The more I work with the K8 stuff the more impressed I am with the
people who got it all to go 6 years ago. (and at how much I've forgotten
but that's another story :=)
If we can get this next step done we're very close to having a working
initram.
And, once you have ram and hit stage2, life is just better all around.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@839 f3766cd6-281f-0410-b1cd-43a5c92072e9
since the box it is on is kinda old.
I realize it is wrong but it is getting there.
The k8 startup is a work of genius. I hope at some point it will be a
work of genius that the rest of us can understand :-)
But it's very impressive code in how it works.
Discussions with AMD: we're in agreement that the structure of this code
will change for the better, but it's helpful to have this audit trail of
changes.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@837 f3766cd6-281f-0410-b1cd-43a5c92072e9
since the box it is on is kinda old.
I realize it is wrong but it is getting there.
The k8 startup is a work of genius. I hope at some point it will be a
work of genius that the rest of us can understand :-)
But it's very impressive code in how it works.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@836 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is the CPU startup code. I'm documenting and cleaning it up
(removing all support for pre-f2 CPUs) and trying to get it to the point
that people can see what's going on. This code is needed for k8 initram.
I'm adding doxygen comments, all errors are mine, and corrections are
welcome.
Signed-off-by: Ronald G. Minnich <rminnich@gmai.com>
Acked-by: Ronald G. Minnich <rminnich@gmai.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@829 f3766cd6-281f-0410-b1cd-43a5c92072e9
We need the sys_info struct in the global variables struct for
cache as ram on k8. The sys_info struct is generally very useful
so it makes sense to start accomodating it.
This patch adds an (empty for now) sys_info struct for geode.
It add sys_info to the global variables struct.
It removes global variables from console.h to a new file,
globalvars.h. Very little code needs to include this file.
This patch is tested on the dbe62 and simnow with no problems.
k8 compilation is now broken but I'm working on it. I'm going through
the eyeballs-bleed code on k8 startup to document it and with any luck
we'll have more functionality by the end of today. But it's hard ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@828 f3766cd6-281f-0410-b1cd-43a5c92072e9
This means that basic resource maps are working, initial hypertransport
setup is working, the amd8111 ISA device is working, config space is
working for all the parts, we can grow the FLASH part address space to
more than 64k, and in general we're having a good time.
Here is the output:
coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting...
(console_loglevel=8)
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: normal/stage2/segment0@0xfff866f0, size 1
LAR: normal/stage2/segment1@0xfff86750, size 18542
LAR: normal/stage2/segment2@0xfff8b010, size 559
LAR: normal/payload/segment0@0xfff8b290, size 18142
LAR: bootblock@0xffff7fc0, size 32768
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: CHECK normal/initram/segment0 @ 0xfff80740
start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004
loadaddress 0x00000000
Entry point is 0xfff80794
Hi there from stage1
stage1 returns
run_file returns with 0
Goal for tomorrow is to get initram done.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@812 f3766cd6-281f-0410-b1cd-43a5c92072e9
Now to start testing.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@810 f3766cd6-281f-0410-b1cd-43a5c92072e9
code now unconditionally pushes an empty pointer to the stack which is a
placeholder for the pointer to global variable storage. That pointer and
the global variable storage are initialized in global_vars_init().
Creating global variables is now a piece of cake. You don't even have to
touch any asm code, just add them to struct global_vars.
Build tested on all targets, boot tested on Qemu.
NOTES:
- The code is not yet MP safe, but that's due to v3 not being MP safe in
general (and the comments contradict the code regarding MP features).
- K8 code now works by accident.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@785 f3766cd6-281f-0410-b1cd-43a5c92072e9
The problem was that gas treated whitespace asargument delimiter.
Removing the whitespace in crtitical places is the most obvious fix.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@727 f3766cd6-281f-0410-b1cd-43a5c92072e9
errata for early silicon and is not mentioned in the public rev guide.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@725 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
it working, then we'll get it pretty.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@704 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@703 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@702 f3766cd6-281f-0410-b1cd-43a5c92072e9
