mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d83abdaf6f
Why? Because the board doesn't use ide support. So you can't compile that in, it's not in the dts. the mainboard Makefile picks the southbridge .c's to use. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1009 f3766cd6-281f-0410-b1cd-43a5c92072e9
154 lines
4.6 KiB
C
154 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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static void pci_init(struct device *dev)
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{
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u16 reg16;
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#if 0
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/* Commented out for now because it will break on some machines. */
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/* Set latency timer to 32. */
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pci_write_config16(dev, 0x1b, 0x20);
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#endif
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/* disable parity error response */
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reg16 = pci_read_config16(dev, 0x3e);
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reg16 &= ~(1 << 0);
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pci_write_config16(dev, 0x3e, reg16);
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, 0x06);
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reg16 |= 0xf900;
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pci_write_config16(dev, 0x06, reg16);
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reg16 = pci_read_config16(dev, 0x1e);
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reg16 |= 0xf900;
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pci_write_config16(dev, 0x1e, reg16);
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}
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static void ich_pci_dev_enable_resources(struct device *dev)
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{
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const struct pci_operations *ops;
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u16 command;
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/* Set the subsystem vendor and device id for mainboard devices */
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ops = ops_pci(dev);
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if (dev->on_mainboard && ops && ops->set_subsystem) {
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printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
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dev_path(dev),
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MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
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MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
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ops->set_subsystem(dev,
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MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
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MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
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}
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#if 0
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/* If we write to PCI_COMMAND, on some systems
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* this will cause the ROM and APICs not being visible
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* anymore.
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*/
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command = pci_read_config16(dev, PCI_COMMAND);
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command |= dev->command;
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printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
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pci_write_config16(dev, PCI_COMMAND, command);
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#endif
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}
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static void ich_pci_bus_enable_resources(struct device *dev)
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{
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u16 ctrl;
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/* enable IO in command register if there is VGA card
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* connected with (even it does not claim IO resource)
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*/
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if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
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dev->command |= PCI_COMMAND_IO;
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ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
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ctrl |= dev->link[0].bridge_ctrl;
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ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
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printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
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pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
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/* This is the reason we need our own pci_bus_enable_resources */
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ich_pci_dev_enable_resources(dev);
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enable_childrens_resources(dev);
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}
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static void set_subsystem(struct device * dev, u16 vendor, u16 device)
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{
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#if 0
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/* Currently disabled because it causes a "BAR 9" memory resource
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* conflict:
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*/
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u32 pci_id;
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printk(BIOS_DEBUG, "Setting PCI bridge subsystem ID\n");
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pci_id = pci_read_config32(dev, 0);
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id );
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#endif
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = set_subsystem,
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};
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/* Desktop */
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/* 82801BA/CA/DB/EB/ER/FB/FR/FW/FRW/GB/GR/GDH/HB/IB/6300ESB/i3100 */
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struct device_operations i82801g_pci = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x244e}}},
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.constructor = default_device_constructor,
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.reset_bus = pci_bus_reset,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = ich_pci_bus_enable_resources,
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.phase6_init = pci_init,
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.ops_pci = &pci_dev_ops_pci,
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};
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/* Mobile / Ultra Mobile */
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/* 82801BAM/CAM/DBL/DBM/FBM/GBM/GHM/GU/HBM/HEM */
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struct device_operations i82801gmu_pci = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x2448}}},
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.constructor = default_device_constructor,
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.reset_bus = pci_bus_reset,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = ich_pci_bus_enable_resources,
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.phase6_init = pci_init,
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.ops_pci = &pci_dev_ops_pci,
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};
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