mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d83abdaf6f
Why? Because the board doesn't use ide support. So you can't compile that in, it's not in the dts. the mainboard Makefile picks the southbridge .c's to use. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1009 f3766cd6-281f-0410-b1cd-43a5c92072e9
382 lines
10 KiB
C
382 lines
10 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <io.h>
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#include <statictree.h>
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#include <config.h>
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#include "i82801gx.h"
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#include "../../../northbridge/intel/i945/ich7.h"
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
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#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
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#endif
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#define NMI_OFF 0
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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* 0x02 - 0010 = Reserved
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* 0x03 - 0011 = IRQ3
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* 0x04 - 0100 = IRQ4
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* 0x05 - 0101 = IRQ5
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* 0x06 - 0110 = IRQ6
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* 0x07 - 0111 = IRQ7
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* 0x08 - 1000 = Reserved
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* 0x09 - 1001 = IRQ9
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* 0x0A - 1010 = IRQ10
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* 0x0B - 1011 = IRQ11
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* 0x0C - 1100 = IRQ12
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* 0x0D - 1101 = Reserved
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* 0x0E - 1110 = IRQ14
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* 0x0F - 1111 = IRQ15
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* PIRQ[n]_ROUT[7] - PIRQ Routing Control
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* 0x80 - The PIRQ is not routed.
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*/
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#define PIRQA 0x03
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#define PIRQB 0x05
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#define PIRQC 0x06
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#define PIRQD 0x07
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#define PIRQE 0x09
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#define PIRQF 0x0A
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#define PIRQG 0x0B
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#define PIRQH 0x0C
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static void i82801gx_enable_apic(struct device *dev)
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{
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int i;
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
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volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
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/* Enable ACPI I/O and power management. */
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pci_write_config8(dev, ACPI_CNTL, 0x80);
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*ioapic_index = 0;
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*ioapic_data = (1 << 25);
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*ioapic_index = 0;
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reg32 = *ioapic_data;
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printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
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if (reg32 != (1 << 25))
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die("APIC Error\n");
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printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
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for (i=0; i<3; i++) {
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*ioapic_index = i;
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printk(BIOS_SPEW, " reg 0x%04x:", i);
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reg32 = *ioapic_data;
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printk(BIOS_SPEW, " 0x%08x\n", reg32);
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}
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*ioapic_index = 3; /* Select Boot Configuration register. */
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*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
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}
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static void i82801gx_enable_serial_irqs(struct device *dev)
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{
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/* Set packet length and toggle silent mode bit for one frame. */
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
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}
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static void i82801gx_pirq_init(struct device * dev)
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{
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pci_write_config8(dev, PIRQA_ROUT, 0x85);
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pci_write_config8(dev, PIRQB_ROUT, 0x87);
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pci_write_config8(dev, PIRQC_ROUT, 0x86);
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pci_write_config8(dev, PIRQD_ROUT, 0x87);
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pci_write_config8(dev, PIRQE_ROUT, 0x80);
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pci_write_config8(dev, PIRQF_ROUT, 0x80);
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pci_write_config8(dev, PIRQG_ROUT, 0x80);
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pci_write_config8(dev, PIRQH_ROUT, 0x85);
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}
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static void i82801gx_power_options(struct device * dev)
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{
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u8 reg8;
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u16 reg16;
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int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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int nmi_option;
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*/
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get_option(&pwr_on, "power_on_after_fail");
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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reg8 &= 0xfe;
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if (pwr_on) {
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reg8 &= ~1;
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} else {
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reg8 |= 1;
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}
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reg8 |= (3 << 4); /* avoid #S4 assertions */
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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printk(BIOS_INFO, "Set power %s after power failure.\n", pwr_on ? "on" : "off");
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/* Set up NMI on errors. */
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reg8 = inb(0x61);
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reg8 &= 0x0f; /* Higher Nibble must be 0 */
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reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
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// reg8 &= ~(1 << 2); /* PCI SERR# Enable */
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reg8 |= (1 << 2); /* PCI SERR# Disable for now */
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outb(reg8, 0x61);
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reg8 = inb(0x70);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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printk_info ("NMI sources enabled.\n");
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reg8 &= ~(1 << 7); /* Set NMI. */
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} else {
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printk_info ("NMI sources disabled.\n");
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reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
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}
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outb(reg8, 0x70);
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// Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~3;
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reg16 |= (1 << 3) | (1 << 5) | (1 << 10);
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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// Set GPIO13 to SCI (?)
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// This might be board specific
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pci_write_config32(dev, 0xb8, 0x08000000);
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}
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void i82801gx_rtc_init(struct device *dev)
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{
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u8 reg8;
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u32 reg32;
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int rtc_failed;
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~RTC_BATTERY_DEAD;
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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}
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printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
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rtc_init(rtc_failed);
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}
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static void enable_hpet(struct device *dev)
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{
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u32 reg32;
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u32 code = (0 & 0x3);
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reg32 = pci_read_config32(dev, GEN_CNTL);
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reg32 |= (1 << 17); /* Enable HPET. */
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/*
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* Bits [16:15] Memory Address Range
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* 00 FED0_0000h - FED0_03FFh
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* 01 FED0_1000h - FED0_13FFh
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* 10 FED0_2000h - FED0_23FFh
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* 11 FED0_3000h - FED0_33FFh
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*/
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reg32 &= ~(3 << 15); /* Clear it */
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reg32 |= (code << 15);
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/* TODO: reg32 is never written to anywhere? */
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printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
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}
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static void i82801gx_lock_smm(struct device *dev)
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{
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void smm_lock(void);
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u8 reg8;
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#if ENABLE_ACPI_MODE_IN_COREBOOT
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printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
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outb(0xe1, 0xb2); // Enable ACPI mode
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printk(BIOS_DEBUG, "done.\n");
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#else
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printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
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outb(0x1e, 0xb2); // Disable ACPI mode
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printk(BIOS_DEBUG, "done.\n");
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#endif
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/* Don't allow evil boot loaders, kernels, or
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* userspace applications to deceive us:
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*/
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smm_lock();
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#if TEST_SMM_FLASH_LOCKDOWN
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/* Now try this: */
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printk(BIOS_DEBUG, "Locking BIOS to RO... ");
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reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
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(reg8&1)?"rw":"ro");
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reg8 &= ~(1 << 0); /* clear BIOSWE */
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pci_write_config8(dev, 0xdc, reg8);
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reg8 |= (1 << 1); /* set BLE */
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pci_write_config8(dev, 0xdc, reg8);
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printk(BIOS_DEBUG, "ok.\n");
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reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
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(reg8&1)?"rw":"ro");
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printk(BIOS_DEBUG, "Writing:\n");
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*(volatile u8 *)0xfff00000 = 0x00;
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printk(BIOS_DEBUG, "Testing:\n");
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reg8 |= (1 << 0); /* set BIOSWE */
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pci_write_config8(dev, 0xdc, reg8);
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reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
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(reg8&1)?"rw":"ro");
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printk(BIOS_DEBUG, "Done.\n");
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#endif
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}
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static void lpc_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
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/* Set the value for PCI command register. */
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pci_write_config16(dev, PCI_COMMAND, 0x000f);
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/* IO APIC initialization. */
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i82801gx_enable_apic(dev);
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i82801gx_enable_serial_irqs(dev);
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/* Setup the PIRQ. */
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i82801gx_pirq_init(dev);
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/* Setup power options. */
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i82801gx_power_options(dev);
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/* Set the state of the GPIO lines. */
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//gpio_init(dev);
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/* Initialize the real time clock. */
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i82801gx_rtc_init(dev);
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/* Initialize ISA DMA. */
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isa_dma_init();
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/* Initialize the High Precision Event Timers, if present. */
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enable_hpet(dev);
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setup_i8259();
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i82801gx_lock_smm(dev);
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}
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static void i82801gx_lpc_read_resources(struct device * dev)
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{
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struct resource *res;
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add an extra subtractive resource for both memory and I/O. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->flags =
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IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->flags =
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IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void i82801gx_lpc_enable_resources(struct device * dev)
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{
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pci_dev_enable_resources(dev);
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enable_childrens_resources(dev);
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}
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static void set_subsystem(struct device * dev, unsigned vendor, unsigned device)
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{
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printk(BIOS_DEBUG, "Setting LPC bridge subsystem ID\n");
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, 0));
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = set_subsystem,
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};
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void i82801gx_enable(struct device * dev);
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/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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struct device_operations ich7_ich7r_ich7dh_lpc = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x27b8}}},
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.constructor = default_device_constructor,
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.reset_bus = pci_bus_reset,
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.phase3_chip_setup_dev = i82801gx_enable,
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.phase3_scan = scan_static_bus,
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.phase4_read_resources = i82801gx_lpc_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = i82801gx_lpc_enable_resources,
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.phase6_init = lpc_init,
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.ops_pci = &pci_ops,
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};
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/* 82801GBM/GU (ICH7-M/ICH7-U) */
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struct device_operations ich7m_ich7u_lpc = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x27b9}}},
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.constructor = default_device_constructor,
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.reset_bus = pci_bus_reset,
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.phase3_chip_setup_dev = i82801gx_enable,
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.phase3_scan = scan_static_bus,
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.phase4_read_resources = i82801gx_lpc_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = i82801gx_lpc_enable_resources,
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.phase6_init = lpc_init,
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.ops_pci = &pci_ops,
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};
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/* 82801GHM (ICH7-M DH) */
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struct device_operations ich7m_dh_lpc = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x27bd}}},
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.constructor = default_device_constructor,
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.reset_bus = pci_bus_reset,
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.phase3_chip_setup_dev = i82801gx_enable,
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.phase3_scan = scan_static_bus,
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.phase4_read_resources = i82801gx_lpc_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = i82801gx_lpc_enable_resources,
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.phase6_init = lpc_init,
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.ops_pci = &pci_ops,
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};
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